Bond Pad Array With Staggered Inner Outer Pads
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Solution Overview
Problem
The challenge is to reduce the pad pitch in complex ICs to increase the number of pads on the chip surface without compromising the space for circuitry or increasing the risk of electro-migration.
Innovation Solution
A bond pad array structure with inner and outer pads, where the inner pads have reduced width metal layers and vias, allowing the outer pads' conductive lines to widen without increasing the risk of electro-migration, and enabling the inner pads to overlap these lines, thus reducing the pad pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pad pitch is decreased to increase the number of pads, then the quantity of pads increases, but the risk of electro-migration increases
Solution Approach 1:
The patent applies different metal layer widths to different regions: inner pads have narrower metal layers while outer pads have wider metal layers. This local differentiation allows the outer pads to carry higher currents without electro-migration, enabling reduced pad pitch while maintaining reliability.
Solution Approach 2:
The patent utilizes multiple metal layers (Mtop, Mtop-1, Mtop-2) stacked vertically to increase the effective conductive cross-section. By distributing current across multiple layers with varying widths, the design achieves higher current capacity in a compact horizontal footprint, enabling smaller pad pitch.
2Power
If the pad pitch is increased to widen conductive lines, then the power supply capability improves, but the number of pads decreases
Solution Approach 1:
The patent compensates for reduced horizontal space by expanding vertically through multiple metal layers. The stacked configuration of Mtop, Mtop-1, and Mtop-2 layers provides increased conductive cross-section area, maintaining power supply capability despite smaller pad pitch.
Solution Approach 2:
The patent assigns different metal layer width configurations to different pad regions based on their current requirements. Outer pads receive wider metal layers for high-power applications, while inner pads use narrower layers, optimizing power distribution across the chip.
3Reliability
If the metal layer width is increased to reduce electro-migration, then the reliability improves, but the space for circuitry decreases
Solution Approach 1:
The patent applies wider metal layers only to outer pads where high current flow occurs, while inner pads use narrower layers. This localized approach provides electro-migration resistance where needed without unnecessarily consuming chip area in other regions.
Solution Approach 2:
The patent achieves increased current capacity by stacking multiple metal layers vertically rather than expanding horizontally. This vertical expansion preserves horizontal space for circuitry while providing sufficient conductive cross-section to prevent electro-migration.
Data Source
AI summary
An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.