Bond Pad Structure Reducing Parasitic Capacitance
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Solution Overview
Problem
Conventional bond pad structures over active circuitry in integrated circuits face challenges in reducing parasitic capacitance, which affects chip performance due to increased mechanical stress during bonding processes.
Innovation Solution
A bond pad structure comprising a conductive pad on a dielectric layer, a conductive frame and electrically floating conductive pieces or plates below, connected via via plugs, which absorb mechanical stress and reduce parasitic capacitance by isolating the active circuitry from bonding forces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reinforced pad structures are employed to counteract mechanical stress during bonding, then bonding over active circuitry becomes feasible, but parasitic capacitance increases which adversely affects chip performance
Solution Approach 1:
The bond pad structure is segmented into multiple conductive layers (first conductive block in second dielectric layer, second conductive block in third dielectric layer, and conductive pad in first dielectric layer) connected by via plugs. This segmentation allows the mechanical stress to be distributed across multiple layers and regions, reducing the stress concentration on any single layer while maintaining bonding reliability. The segmented structure also reduces parasitic capacitance by separating the conductive elements in the vertical dimension.
Solution Approach 2:
The invention transitions from a conventional two-dimensional pad structure to a three-dimensional multi-layer structure. Conductive blocks are formed in different dielectric layers (second and third dielectric layers below the first dielectric layer) and connected through via plugs, creating a vertical stacking arrangement. This dimensional change allows stress distribution in the vertical direction and reduces the parasitic capacitance footprint on the chip surface.
2Reliability
If bond pads are arranged in rows along four chip sides with excluded area for circuit patterns, then circuit damage risk is reduced, but chip size increases
Solution Approach 1:
The bond pad structure extends into the vertical dimension with conductive blocks formed in second and third dielectric layers below the conductive pad. This multi-layer configuration allows the bond pad to provide mechanical reinforcement and stress absorption in the vertical direction, enabling bond pads to be placed over active circuitry without increasing the horizontal chip area.
Solution Approach 2:
The reinforced pad structure provides localized mechanical support and stress absorption specifically at the bond pad location, while the surrounding active circuitry maintains its normal design. The conductive blocks in lower dielectric layers are strategically positioned to provide reinforcement only where needed, allowing circuit patterns to be densely packed in non-pad regions.
3Ease of manufacture
If conventional bond pad structures are used, then manufacturing is simpler, but mechanical stress during bonding damages underlying circuit structures
Solution Approach 1:
The bond pad is segmented into multiple conductive blocks connected by via plugs, with each layer providing specific mechanical support functions. This segmentation allows the structure to absorb and distribute bonding-induced mechanical stress across multiple regions, protecting the underlying active circuitry while maintaining a manufacturing process that integrates with existing multi-layer fabrication techniques.
Data Source
AI summary
A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad.