Bond-Pad Charging Protection for Reference Transistor Test Structures
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Solution Overview
Problem
Transistor test structures in IC manufacturing are vulnerable to plasma charging damage during the backend process, which can alter their characteristics and make them differ from actual circuit transistors, and existing protection methods like protection diodes may not always be effective.
Innovation Solution
A bond-pad design that protects all terminals of reference transistor test structures, minimizing layout space and gate oxide stress, using a 6-metal-layer CMOS process and simulations based on multiple-terminal and ILD charging models to ensure charging-free performance during plasma-involved manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large-size gate bond pads are used for measurement purposes, then measurement accuracy is improved, but plasma charging damage increases
Solution Approach 1:
The bond pad structure is segmented into multiple metal layers (M1-M6) with different functions. The lower layers (M1-M4) provide measurement access with controlled sizes, while the top layer (M6) provides the large-area protection pad. This segmentation allows each layer to optimize for its specific function without compromising the other.
Solution Approach 2:
The patent introduces an intermediary protection diode connected between the gate bond pad and the large-area M6 bond pad. This diode acts as a mediator that safely dissipates plasma-induced charges before they can damage the gate oxide, while still allowing the large M6 pad to provide measurement accuracy.
2Reliability
If protection diodes are added at the bond pad to prevent charging damage, then transistor protection is improved, but device complexity increases
Solution Approach 1:
The protection diode is merged with the existing bond pad structure by sharing the M6 bond pad area and utilizing standard CMOS diode implementations. The diode cathode connects to the gate bond pad while the anode connects to the M6 pad, combining protection functionality with the measurement structure without requiring completely separate protection circuitry.
3Reliability
If multiple metal layers are used for bond pad protection, then charging protection effectiveness is improved, but layout space usage increases
Solution Approach 1:
The patent transitions from a single-plane bond pad design to a multi-layer vertical structure. The large M6 bond pad extends in the planar dimension for protection, while the vertical stacking of M1-M6 layers provides the protection mechanism without proportionally increasing the lateral footprint. The vias connecting layers utilize vertical space efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed bond-pad design effectively prevents plasma charging damage, maintaining transistor characteristics and ensuring accurate measurement by keeping transistors immune to charging effects, as verified by experiments and simulations, while minimizing layout space and gate oxide stress.
Implementation Method 1
plasma charging damage during the plasma-involved BE IC manufacturing process
Implementation Method 2
introducing strong process charging effect to degrade transistor characteristics
Data Source
AI summary
A method for preparing a reference transistor test structure having a transistor with multiple terminals is provided. The method may include placing a set of bond pads at a first layer of the reference transistor test structure with each of the bond pads connecting to its corresponding terminal of the transistor, wherein the first layer of the reference transistor test structure is an uppermost metal layer. The method may further include placing a first protection device at a second layer of the reference transistor test structure and connecting the first protection device to at least one of the terminals of the transistor, wherein the second layer is a lowermost metal layer.