Bond Pad Integrated Over-Voltage Clamp for ESD Protection

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Solution Overview

Problem

High-voltage integrated circuits (ICs) are vulnerable to electrical overstress and electrostatic discharge, leading to damage and reliability issues due to the sensitivity of conventional MOS technologies, which are difficult to protect effectively with existing over-voltage clamp solutions, especially in mixed-signal applications where space and cost constraints are significant.

Innovation Solution

The development of small-footprint over-voltage clamp structures integrated into high-voltage bond pads, utilizing modified planar MOS devices with additional doped regions for increased conductivity modulation and improved electric field control, allowing for efficient shunting of currents during over-voltage conditions without soft-failure leakage, and optimized current distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional high-voltage MOS structures are used for over-voltage protection, then the clamp circuits can operate at relatively large voltages, but they are very sensitive to ESD-induced damage and exhibit soft failure with elevated leakage currents

Engineering Contradiction:

ImproveESD robustnessVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent modifies the electrical parameters of the MOS structure by introducing additional doped regions (p+ and n+ regions) adjacent to the gate structure. This changes the conductivity modulation and electric field distribution in the depletion region, enabling the clamp to withstand ESD stress without soft failure and maintaining low leakage currents below 1 nA after stress events

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The invention creates a composite doped region structure within the MOS clamp device, combining multiple doping types (p-type and n-type regions) in close proximity. This composite structure enables both high-voltage operation and ESD robustness by controlling carrier distribution and reducing surface junction heating that causes soft failure

Inventive Principle:

Principle #40Composite materials

2Reliability

If multiple low-voltage devices are stacked to implement higher-voltage ESD switch, then ESD protection capability is improved, but large area is required for high-voltage IO terminals and clamp implementation

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the ESD protection function directly into the bond pad structure itself, integrating the clamp circuit within the existing bond pad footprint. This eliminates the need for separate ESD protection devices and reduces the overall chip area required for ESD protection while maintaining robustness against ESD stress

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If isolation layers are used to isolate low-voltage devices from substrate for high-voltage clamp implementation, then ESD protection is improved, but significant leakage buildup occurs due to large area reverse-biased junctions

Engineering Contradiction:

ImproveESD protectionVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the doping parameters and spatial distribution of doped regions to control the electric field and carrier concentration in the depletion region. This enables the clamp to block leakage currents effectively while maintaining ESD protection capability, achieving leakage currents below 1 nA after ESD stress events without requiring large-area isolation structures

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides enhanced ESD robustness, reduces device area, and maintains high energy efficiency by effectively shunting currents during over-voltage events, preventing damage and ensuring reliable operation in high-voltage ICs, particularly in advanced automotive, medical, and industrial applications.

Implementation Method 1

utilizing modified planar MOS devices with additional doped regions for increased conductivity modulation

Methodology Applied

Scientific EffectConductivity modulation:

Implementation Method 2

the clamp circuits should not affect operation of the full IC system. Thus, the current flow through the clamp device is close to zero at voltages up to a trigger voltage level at which current conduction occurs

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)