Bond Pad Structure for Misalignment-Tolerant Die Bonding
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Solution Overview
Problem
Existing wafer bonding technologies face challenges in reducing the size and misalignment effects of bond pads and bond pad vias, which can lead to increased contact resistance and defects in die and package structures.
Innovation Solution
The method involves forming bond pad vias and bond pads in separate processing steps, allowing for closer spacing and smaller sizes, and using direct bonding techniques to align and bond the pads, even with misalignment, by forming bond pads with varying widths to ensure complete contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If bond pads and bond pad vias are formed in separate processing steps, then the size and separation of features can be reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent divides the formation of bond pads and bond pad vias into separate processing steps. Bond pad vias are formed first through the dielectric layer, followed by a subsequent step to form bond pads on top of the vias. This segmentation allows each feature to be optimized independently, reducing their overall size and separation while maintaining manufacturing feasibility through structured process separation.
2Reliability
If bond pads are formed with varying widths, then misalignment effects can be reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric bond pad designs where pads on one die have different widths compared to their corresponding pads on the bonded die. This asymmetry is strategically designed so that the larger pad area compensates for potential misalignment during bonding, ensuring complete contact between bonding surfaces. The varying widths are precisely controlled through photolithography and etching processes to achieve the desired compensation effect.
3Productivity
If feature spacing is reduced, then routing density increases, but the risk of defects increases
Solution Approach 1:
The patent reduces feature spacing primarily in the horizontal plane while maintaining adequate vertical separation through multi-layer dielectric structures. By utilizing the third dimension (vertical stacking of dielectric layers), the design achieves high routing density without compromising the reliability of closely spaced features. The separate formation steps also allow for optimized via dimensions that prevent bridging defects even when horizontal spacing is minimized.
Data Source
AI summary
A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.