Bond Pad Protective Layer for Fluorine Etch Reliability

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Solution Overview

Problem

During integrated chip fabrication, bond pads are damaged by fluorine-based etching byproducts, leading to electrical failures and poor adhesion with overlying conductors, and the use of non-fluorine based etchants to remove these byproducts can damage the bond pad and slow down the fabrication process, violating q-time requirements.

Innovation Solution

A protective layer is formed over the bond pad, which has high etching selectivity with respect to the passivation and bond pad materials, allowing for the removal of etching byproducts without damaging the bond pad, using a dry etching process followed by a wet etching process to expose the bond pad surface, thereby preventing damage and ensuring smoothness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fluorine-based etching is used to form openings through passivation layers, then etching efficiency is improved, but etching byproducts damage the bond pad causing electrical failures and poor adhesion

Engineering Contradiction:
Improveetching efficiencyVSAvoidbond pad electrical reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A protective layer is introduced as an intermediary between the fluorine-based etching process and the bond pad. This protective layer selectively resists fluorine-based etchants, allowing the etching to proceed efficiently through passivation layers while preventing direct contact between the etchant and bond pad, thus eliminating damaging byproducts like AlF3 formation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the bond pad structure by adding a separate protective layer component. This segmentation allows different regions to have different functions: the passivation layers are etched away to form openings, while the protective layer remains intact to shield the bond pad during the etching process

Inventive Principle:
Principle #1Segmentation

2Reliability

If non-fluorine based etchants are used to remove etching byproducts from the bond pad, then bond pad damage is reduced, but the fabrication process time increases violating q-time requirements

Engineering Contradiction:
Improvebond pad integrityVSAvoidfabrication process time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The protective layer is applied in advance before the fluorine-based etching process. This preliminary action prevents the formation of harmful byproducts on the bond pad surface, eliminating the need for subsequent cleaning steps with non-fluorine based etchants and dedicated chambers, thus maintaining both bond pad integrity and fabrication throughput

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a protective layer is added over the bond pad, then bond pad reliability is improved, but device structure complexity increases

Engineering Contradiction:
Improvebond pad reliabilityVSAvoidbond pad structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective layer serves multiple functions simultaneously: it acts as a barrier during fluorine-based etching to prevent byproduct formation, provides a surface for subsequent conductor deposition, and can be selectively removed to expose the bond pad. This multi-functionality justifies the added structural element by delivering multiple benefits from a single component

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The protective layer prevents the formation of etching byproducts on the bond pad, maintains bond pad integrity, and improves throughput by eliminating the need for a dedicated chamber for non-fluorine based etching, ensuring reliable electrical connections and adherence to q-time requirements.

Implementation Method 1

A protective layer is formed over the bond pad, which has high etching selectivity with respect to the passivation and bond pad materials

Methodology Applied
Scientific EffectEtching selectivity:

Implementation Method 2

using a dry etching process followed by a wet etching process to expose the bond pad surface

Methodology Applied
Scientific EffectDry etching:

Implementation Method 3

using a dry etching process followed by a wet etching process to expose the bond pad surface

Methodology Applied
Scientific EffectWet etching:

Data Source

PatentUS12165996B2Bond pad with enhanced reliability
Publication Date: 2024.12.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12165996B2 patent drawing
  • US12165996B2 patent drawing
  • US12165996B2 patent drawing

AI summary

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of interconnects disposed within a dielectric structure over a substrate. A conductor is disposed over at least one of the plurality of interconnects. A protective layer is disposed on the conductor and a mask layer is disposed on the protective layer. One or more passivation layers are disposed on the mask layer. The protective layer, the mask layer, and the one or more passivation layers respectively have one or more sidewalls directly over the conductor.