Bond Pad Film Structure for Fluorine-Resistant Chip Dicing

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Solution Overview

Problem

Traditional dicing processes for integrated chip fabrication can cause mechanical stress and result in increased resistance of bond pads due to damage from etchants and fluorine-based gases, leading to higher power consumption and reduced performance.

Innovation Solution

The method involves forming a bond pad stack with a titanium contact layer that is resistant to fluorine-based etchants, using a first masking layer to protect the contact layer during etching, and employing deep trenches filled with dielectric material to separate integrated chip die using a fluorine-based gas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional dicing processes are used to separate integrated chip die, then productivity is improved, but the bond pad contact layer is damaged by etchants and fluorine-based gases, increasing resistance and power consumption

Engineering Contradiction:
Improvechip fabrication efficiencyVSAvoidbond pad resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A sacrificial masking layer is introduced as an intermediary between the fluorine-based etchant and the bond pad contact layer. This masking layer absorbs the harmful effects of the etchant, preventing direct damage to the contact layer while enabling the dicing process to proceed effectively

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the potentially harmful fluorine-based etching process into a beneficial tool by using it to create deep trenches for chip separation, while the sacrificial masking layer protects the contact layer. The harmful etchant becomes useful when directed at the masking layer rather than the contact layer

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Productivity

If fluorine-based gases are used to remove dielectric material and separate chip die, then productivity is improved, but byproducts are formed on the contact layer, increasing resistance and power consumption

Engineering Contradiction:
Improvechip separation efficiencyVSAvoidfluorine byproducts on contact layer
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The sacrificial masking layer serves as a mediator that intercepts fluorine-based gases during the dielectric removal process. It absorbs the fluorine byproducts that would otherwise deposit on and damage the bond pad contact layer, enabling clean chip separation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the harmful interaction between fluorine-based gases and the contact layer by removing the contact layer from the etching zone. The sacrificial masking layer is positioned between the gas and contact layer, extracting the harmful fluorine byproducts before they can reach the contact layer

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If mechanical dicing is used to separate chip die, then productivity is improved, but mechanical stress damages the bond pad contact layer, increasing resistance

Engineering Contradiction:
Improvechip separation rateVSAvoidcontact layer integrity
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

The sacrificial masking layer is applied in advance before the dicing process. This preliminary protective action ensures that when mechanical stress occurs during dicing, the contact layer is already shielded, preventing damage before it can occur

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces damage to the bond pad contact layer, maintains low resistance (less than 20 ohms), and minimizes the formation of byproducts from fluorine-based gases, thereby improving the performance and reducing power consumption of integrated chips.

Implementation Method 1

employing deep trenches filled with dielectric material to separate integrated chip die using a fluorine-based gas

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

forming a bond pad stack with a titanium contact layer that is resistant to fluorine-based etchants

Methodology Applied
Scientific EffectChemical resistance:

Data Source

PatentUS12249586B2Film structure for bond pad
Publication Date: 2025.03.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12249586B2 patent drawing
  • US12249586B2 patent drawing
  • US12249586B2 patent drawing

AI summary

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.