Bond-Pad Structure for High-Voltage MOSFETs
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Solution Overview
Problem
The large size of bonding pads on semiconductor devices leads to significant parasitic capacitance, which negatively impacts the performance of connected devices by increasing electrical interference and reducing efficiency.
Innovation Solution
A bonding-pad structure is designed with interposed polysilicon plates encapsulated in dielectric layers between the metal bonding pad and the semiconductor substrate, effectively reducing capacitance by creating electrical shielding and optimizing the placement of the polysilicon plates to minimize the distance between them and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the bonding pad is made large to facilitate wire and bump connections, then the ease of operation is improved, but the parasitic capacitance increases
Solution Approach 1:
A polysilicon plate is introduced as an intermediary element between the metal bonding pad and the semiconductor substrate. This intermediate structure serves as a shielding plate that reduces the parasitic capacitance between the bonding pad and the substrate while maintaining the bonding pad's large area for easy connection. The polysilicon plate is conductively coupled to the source terminal, creating an equipotential region that minimizes capacitive coupling.
Solution Approach 2:
The invention changes the electrical parameters of the bonding pad structure by introducing a conductively coupled polysilicon plate. This modification alters the capacitance characteristics by creating a shielded configuration, where the polysilicon plate acts as a reference potential surface that reduces the effective capacitance between the bonding pad and the substrate.
2Area of stationary object
If the bonding pad area is increased to accommodate larger connection structures, then the ease of operation is improved, but the parasitic electrical parameters worsen
Solution Approach 1:
The polysilicon plate serves as a mediator between the large-area bonding pad and the substrate. By positioning this intermediate conductive structure between the bonding pad and substrate and coupling it to the source terminal, the parasitic electrical parameters are reduced while the bonding pad maintains its large area for easy connection.
Solution Approach 2:
The invention addresses the area-capacitance tradeoff by moving to a vertical dimension. Instead of reducing the bonding pad area, a polysilicon plate is positioned in the vertical space between the bonding pad and substrate, creating a three-dimensional shielding structure that reduces parasitic capacitance without affecting the horizontal bonding pad area.
3Ease of operation
If the bonding pad is made large for external circuit connection, then the ease of operation is improved, but device performance deteriorates due to increased parasitic capacitance
Solution Approach 1:
The polysilicon plate acts as a mediator that reconciles the conflict between ease of connection and device performance. By introducing this intermediate shielding structure conductively coupled to the source terminal, the bonding pad can remain large for easy wire and bump connections while the parasitic capacitance is reduced, thereby maintaining device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the parasitic capacitance between the metal bonding pad and the semiconductor substrate, enhancing the performance of high-voltage MOSFETs by minimizing electrical interference and leakage current.
Implementation Method 1
The first and second dielectric layers encapsulate the first polysilicon plate, thereby electrically isolating the first polysilicon plate from the semiconductor substrate
Implementation Method 2
A bonding-pad structure is designed with interposed polysilicon plates encapsulated in dielectric layers between the metal bonding pad and the semiconductor substrate, effectively reducing capacitance by creating electrical shielding
Implementation Method 3
A second polysilicon plate is disposed on top of the second dielectric layer. The second polysilicon plate is conductively coupled to a source of the high-voltage MOSFET
Data Source
AI summary
Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.