Bond Pad Protective Layer for Fluorine Etch Damage Control
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Solution Overview
Problem
During integrated chip fabrication, bond pads are prone to damage from fluorine-based etching byproducts, leading to electrical failures and reduced reliability due to the formation of compounds like AlOH3 and 3HF, and subsequent use of non-fluorine based etchants can cause surface roughness and adhesion issues, slowing down the process and increasing costs.
Innovation Solution
A protective layer is formed over the bond pad, allowing for a dry etching process without damaging the pad and preventing fluorine-metal byproducts from forming on it, followed by a wet etching process to remove the protective layer, which exposes the bond pad with minimal damage, ensuring a smooth surface and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fluorine-based etching is used to form openings in passivation layers, then etching performance is improved, but fluorine-metal byproducts form on the bond pad causing electrical failures
Solution Approach 1:
A protective layer is introduced as an intermediary between the bond pad and the fluorine-based etching process. This protective layer receives the fluorine-based etchant, allowing high-performance fluorine-based etching to proceed while preventing fluorine-metal byproducts from forming on the bond pad surface.
Solution Approach 2:
The protective layer is deposited on the bond pad before the fluorine-based etching process. This preliminary action ensures that when fluorine-based etchant is later applied to form openings in passivation layers, the bond pad is already protected from byproduct formation.
2Reliability
If non-fluorine based etchants are used to remove byproducts, then bond pad damage is reduced, but surface roughness and adhesion issues occur
Solution Approach 1:
The protective layer serves as a mediator that differentially interacts with etchants. It allows fluorine-based etchants to etch passivation layers effectively while being selectively removed by non-fluorine based etchants, protecting the bond pad surface from damage and maintaining smoothness.
Solution Approach 2:
The protective layer provides localized protection specifically where needed (on the bond pad and surrounding areas) while allowing the etching process to proceed in other regions. The selective removal of the protective layer then exposes only the necessary areas with minimal damage.
3Reliability
If multiple etching processes are used to prevent byproducts, then reliability is improved, but fabrication time and cost increase
Solution Approach 1:
The protective layer is deposited once before the etching sequence, establishing protection in advance. This preliminary action eliminates the need for repeated protective measures or complex byproduct removal procedures, streamlining the overall process.
Solution Approach 2:
The protective layer enables changing the etching parameters - specifically, allowing the use of fluorine-based etchants at optimal concentrations and conditions that would otherwise be too aggressive for direct contact with the bond pad, thereby improving reliability without excessive process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents the formation of damaging byproducts on the bond pad, maintains its smoothness, and enhances electrical connections, thereby improving the reliability and throughput of the integrated chip fabrication process while meeting q-time requirements.
Implementation Method 1
A protective layer is formed over the bond pad, allowing for a dry etching process without damaging the pad and preventing fluorine-metal byproducts from forming on it
Implementation Method 2
followed by a wet etching process to remove the protective layer, which exposes the bond pad with minimal damage, ensuring a smooth surface
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive feature disposed over a dielectric structure on a substrate. A first layer is arranged on peripheral regions of the conductive feature. A second layer has a bottommost surface arranged on the first layer. The second layer includes a material that etches at a higher rate than the first layer when exposed to a first etchant and that etches at a lower rate than the first layer when exposed to a second etchant. An additional conductive feature extends through the first layer and the second layer to contact the conductive feature.