Bond Pad Structure with Segmented Metal Layers for Stress Isolation
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Solution Overview
Problem
Existing bond pad structures in integrated circuit packages prohibit the placement of active or passive devices underneath due to package stress and potential damage, necessitating a device-free area that increases chip size and design costs.
Innovation Solution
A bond pad structure featuring a patterned metal layer with an annular metal layer and evenly arranged metal blocks, connected only through the annular layer, allowing for reduced stress transmission and enabling device placement beneath the bond pad by eliminating vias between the metal blocks and lower layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bond pad structure with multiple metal layers and vias is used, then the connection between metal layers is convenient and reliable, but package stress is transmitted to devices underneath, prohibiting device placement in the area below the bond pad
Solution Approach 1:
The bond pad structure is divided into multiple independent metal layers (first, second, and third metal layers) with different connection patterns. The second metal layer is segmented into an annular metal layer and metal blocks, where the annular layer connects to lower layers via vias while the metal blocks do not, creating zones with different stress transmission characteristics
Solution Approach 2:
Different regions of the second metal layer are designed with different connection properties: the annular metal layer maintains via connections to lower layers for structural support and electrical connection, while the metal blocks are isolated from lower layers to create stress-free zones. This local differentiation allows simultaneous stress reduction and connection reliability
2Reliability
If a device-free region is designed under the bond pad structure to prevent stress damage, then device reliability is protected, but the required chip area increases due to the prohibited region
Solution Approach 1:
Instead of creating a device-free region underneath the bond pad, the invention inverts the approach by creating stress-free zones within the bond pad structure itself through the metal blocks that are isolated from lower layers, allowing devices to be placed underneath while protecting them from stress
Solution Approach 2:
The solution moves from a two-dimensional device-free area constraint to a three-dimensional structural design where the vertical stacking of metal layers with selective via connections creates stress management capabilities within the bond pad footprint, enabling device placement in the previously prohibited area
Data Source
AI summary
A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed.