Bond Pad Layout for Thin Shingled Memory Die Stacks

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Solution Overview

Problem

Current semiconductor die stacking in memory devices experiences stress-related failures due to bending forces during manufacturing, limiting the thickness of dies to 50 μm or greater to meet industry standards, which restricts the ability to increase memory density or reduce package size.

Innovation Solution

The semiconductor dies are stacked in a shingled configuration with bond pads oriented perpendicular to the slits, reducing bending stresses and allowing for thinner substrates of 40 μm or less, while maintaining a high success rate in bending tests, enabling more dies to be stacked or a smaller package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor dies are stacked in a shingled arrangement with bond pads parallel to slits, then electrical connections between dies are facilitated, but bending stresses cause die failure during manufacturing

Engineering Contradiction:
Improvedie connection reliabilityVSAvoiddie bending strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent changes the symmetric alignment of bond pads relative to slits by orienting bond pads perpendicular to the slit direction. This asymmetric configuration alters the stress distribution pattern during bending, preventing stress concentration at slit-bond pad intersections and thereby reducing die failure during manufacturing processes.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent modifies the geometric parameter of bond pad orientation from parallel to perpendicular relative to the slit direction. This parameter change fundamentally alters the mechanical stress distribution in the die substrate during bending, enabling thinner dies to withstand manufacturing stresses while maintaining electrical connectivity.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If semiconductor die thickness is reduced to increase memory density, then package size can be reduced or more dies stacked, but bending test success rate drops below industry standards

Engineering Contradiction:
Improvememory densityVSAvoidbending test success rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

By orienting bond pads perpendicular to slits rather than parallel, the patent creates an asymmetric stress distribution that prevents stress concentration points. This allows thinner dies to maintain structural integrity during bending tests, achieving the required 99.5% success rate while enabling reduced die thickness for increased memory density.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent changes the orientation parameter of bond pads relative to slits, which fundamentally alters the mechanical behavior of thin dies under bending stress. This parameter modification enables dies thinner than 50 μm to pass industry bending tests, thereby allowing increased memory density through stacking more thin dies.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If bond pads are oriented parallel to slits for easier electrical connections, then wiring complexity is reduced, but stress concentration at bond pad locations increases

Engineering Contradiction:
Improvewiring complexityVSAvoidstress concentration
Core Design Contradiction:
Device complexityVSStress or pressure

Solution Approach 1:

The patent introduces asymmetry in the bond pad-slit geometric relationship by orienting bond pads perpendicular to slits. This asymmetric arrangement eliminates the stress concentration that occurs when bond pads are parallel to slits, as the perpendicular orientation ensures that bending stresses are distributed uniformly across the die substrate rather than concentrating at bond pad locations.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS11876068B2Bond pad connection layout
Publication Date: 2024.01.16 LODESTAR LICENSING GROUP LLC
  • US11876068B2 patent drawing
  • US11876068B2 patent drawing
  • US11876068B2 patent drawing

AI summary

A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.