Bond Pad Stack via Removal and Composite ILD for Crack Prevention
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Solution Overview
Problem
Conventional wire bonding techniques in integrated circuits cause stress leading to cracks in the inner dielectric layer, which can result in current leakage and performance degradation, limiting the placement of active circuit elements beneath bond pads due to increased risk of cracking.
Innovation Solution
A bond pad stack design with improved layout and inner layer dielectric materials, including a layer of silicon nitride over silicon oxide, reduces stress concentration points by removing vias under the passivation opening and using a composite dielectric layer to enhance toughness, allowing for active circuitry placement beneath bond pads without additional mask layers or process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire bonding techniques are used with standard bond pad stacks, then electrical connection is achieved, but stress causes cracks in the inner dielectric layer leading to current leakage and performance degradation
Solution Approach 1:
The patent applies composite materials by combining silicon nitride and silicon oxide in a layered ILD structure. The silicon nitride layer (50-150 nm thick) is deposited over the silicon oxide ILD layer, creating a composite structure where silicon nitride provides superior mechanical strength and stress resistance. This composite ILD structure prevents crack propagation into the active circuitry while maintaining electrical isolation, directly resolving the reliability issue caused by conventional single-material ILD layers.
Solution Approach 2:
The patent extracts removes vias from the bond pad region by configuring the bond pad such that no vias are present in the area directly beneath the passivation opening. This elimination of vias removes stress concentration points and discontinuities in the ILD layer, preventing crack initiation and propagation during wire bonding. The bond pad is designed to extend beyond the underlying metal layer without requiring via connections in the critical stress zone.
2Reliability
If bond pads occupy significant surface area to prevent cracking, then reliability improves, but active circuit placement flexibility decreases and die size increases
Solution Approach 1:
The composite ILD structure with silicon nitride provides enhanced mechanical strength and crack resistance, enabling the use of smaller, more targeted bond pad regions without compromising reliability. This allows active circuit elements to be placed in previously restricted areas beneath and around bond pads, increasing placement flexibility and reducing overall die size while maintaining protection against crack propagation.
3Reliability
If an extra passivation nitride layer is added over the upper metal layer (as in FIG. 2 design), then robustness against cracking improves, but manufacturing complexity and cost increase due to additional mask layers
Solution Approach 1:
The patent extracts the need for an additional passivation layer by achieving crack protection through the composite ILD structure and via removal strategy alone. The silicon nitride layer within the ILD, combined with the absence of vias under the bond pad, provides sufficient mechanical reinforcement without requiring the extra upper passivation nitride layer. This eliminates the associated additional mask layer and process steps, reducing manufacturing complexity while maintaining robustness.
Solution Approach 2:
The composite ILD structure with silicon nitride provides the necessary mechanical strength and crack resistance that would otherwise require an additional upper passivation layer. The layered composite material system achieves the same protective function with fewer process steps, as the silicon nitride within the ILD structure provides reinforcement throughout the dielectric layer rather than just at the surface.
Data Source
AI summary
A combination of layout improvements and inner layer dielectric (ILD) material improvements provides a bond pad stack that is robust for both gold (Au) and copper (Cu) wires in circuits with only one or two pad metal layers. The layout improvements involve removing all vias between the top metal layer and the metal layers below top metal in the area under the passivation opening (where probe tips and the bond wire are placed). This allows for a more homogenous material without via discontinuities, thereby reducing stress concentration points in the ILD. The ILD material improvement involves adding a layer of silicon nitride in addition to the silicon oxide layer. Traditionally, the ILD consists of either spun-on or high density plasma (HDP) oxides. The growth of the thin layer of silicon nitride over the oxide on the topmost ILD layer provides a composite of significantly increased toughness and prevents cracks or other damage from propagating into the underlying active circuits and routing.