Bond Pad Stress Buffer for Low-k Dielectric Reliability
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Solution Overview
Problem
Semiconductor bond pad structures using extreme low-k dielectric materials face mechanical weakness and reliability issues due to cracking and peeling under mechanical and thermal stresses, affecting device performance and reliability as device geometries miniaturize.
Innovation Solution
A dual damascene structure is formed with a stress buffer layer embedded in the bond pad, using existing manufacturing equipment, where the second insulating layer is positioned substantially in the middle of the trench opening to act as a stress buffer, resisting cracking and peeling during bonding, manufacturing, and thermal cycling processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If extreme low-k dielectric materials are used to reduce RC delay and parasitic capacitances, then chip speed-power product is improved, but mechanical strength decreases causing cracking and peeling under mechanical and thermal stresses
Solution Approach 1:
The patent uses a composite structure combining extreme low-k dielectric material with a stress buffer layer made of different material (such as silicon oxide or silicon nitride). This composite approach allows the ELK material to provide low RC delay while the stress buffer layer provides mechanical strength and stress management, resolving the contradiction between speed improvement and mechanical weakness
Solution Approach 2:
The stress buffer layer acts as an intermediary between the extreme low-k dielectric material and the underlying structures. It mediates the mechanical stresses and thermal expansion differences, preventing cracks from propagating through the ELK layer while allowing the ELK material to maintain its electrical performance benefits
2Reliability
If extreme low-k dielectric materials are used to reduce parasitic capacitances, then RC time constant is reduced, but reliability decreases due to susceptibility to cracking during manufacturing and thermal cycling
Solution Approach 1:
The stress buffer layer is placed beforehand beneath the extreme low-k dielectric material to cushion and absorb mechanical stresses and thermal expansion forces before they can reach and crack the ELK layer. This preventive measure ensures the ELK material maintains its low RC characteristics while the buffer layer protects against reliability-degrading cracks during manufacturing and thermal cycling
3Ease of operation
If bond pad structure is subjected to bonding processes to achieve device functionality, then device performance is achieved, but mechanical stress causes defect formation and cracking in underlying layers
Solution Approach 1:
The stress buffer layer serves as an intermediary that absorbs and distributes the mechanical stress applied during bonding processes. It protects the underlying extreme low-k dielectric and inter-metal dielectric layers from direct stress concentration, allowing bonding operations to proceed while preventing defect formation and cracking in the vulnerable ELK structures
Data Source
AI summary
An integrated circuit structure includes a substrate, and a first metal layer over the substrate. The integrated circuit structure further includes a second insulating layer over the first metal layer, the second insulating layer having a damascene opening and two via openings. The damascene opening has a first depth. The two via openings have a second depth greater than the first depth. The integrated circuit structure further includes a stress buffer having a flat upper surface extending from a first side of the stress buffer to a second side of the stress buffer, the first side and second side being parallel, the stress buffer having a thickness between the upper surface of the stress buffer and the first metal layer, the thickness being less than the second depth and greater than the first depth. The integrated circuit structure further includes a second metal layer over the stress buffer.