Bond Pad Design for Reducing Package Stress in Flip-Chip
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Solution Overview
Problem
The difference in coefficient of thermal expansion between integrated circuit chips and package substrates leads to stress-induced warpage, bump cracking, and delamination of low-k dielectric layers in flip-chip bonding structures, particularly at the corners of the chip, despite the use of underfill materials.
Innovation Solution
Increasing the size of bond pads relative to bump balls, with an enclosure greater than about −1 μm, reduces the stress imparted to the interconnect structure, thereby enhancing the reliability of the flip-chip package by minimizing delamination and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bond pad sizes are used in flip-chip bonding, then manufacturing processes are simpler, but stress-induced warpage and delamination occur due to CTE mismatch
Solution Approach 1:
The patent applies parameter changes by modifying the bond pad dimensions (width and length) to create an enclosure greater than −1 μm. This dimensional adjustment changes the mechanical properties of the bond pad structure, enabling it to better withstand thermal expansion stresses without requiring fundamental design reconfiguration or additional manufacturing steps.
2Reliability
If bond pad size is increased to reduce stress, then reliability improves, but chip area utilization decreases
Solution Approach 1:
The patent optimizes the balance between bond pad size and chip area by specifying an enclosure greater than −1 μm. This parameter threshold ensures sufficient stress distribution capability while minimizing the area consumed by bond pads, thereby maintaining high chip area utilization for active devices.
3Reliability
If underfill is used to protect bump balls, then bump cracking is reduced, but delamination of low-k dielectric layers still occurs
Solution Approach 1:
The patent applies local quality by enhancing the specific region around the bond pad (the enclosure area) to provide localized stress relief. This localized structural modification addresses the root cause of delamination at the bond pad interface without affecting other regions of the chip, allowing underfill to effectively protect bump balls while the bond pad enclosure protects low-k dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased size of bond pads significantly reduces stress on the interconnect structure, improving the reliability of the flip-chip package by lowering the likelihood of delamination and warpage, without requiring additional lithography steps.
Implementation Method 1
the coefficient of thermal expansion (CTE) of IC chip 100 is significantly different from that of package substrate 102. For example, the CTE of IC chip 100 may be about 3 ppm/° C., while the CTE of package substrate 102 may be about 15 ppm/° C. Due to the difference in CTEs, stresses are generated inside IC chip 100 and package substrate 102
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first direction parallel to the front surface of the semiconductor substrate. A bump ball is over the bond pad, wherein the bump ball has a diameter in the first direction, and wherein an enclosure of the first dimension and the diameter is greater than about −1 μm.