Bond Pad Film Structure With Titanium Etch Protection

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Solution Overview

Problem

Traditional dicing processes for integrated chip fabrication, particularly for small-sized chips, result in mechanical stress and increased resistance of bond pads due to damage from fluorine-based etchants, leading to higher power consumption and reduced performance.

Innovation Solution

A method of forming integrated chip die with a bond pad structure that includes a titanium contact layer resistant to fluorine-based etchants, using a masking layer to protect the contact layer during etching and patterning, thereby reducing damage and maintaining low resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional dicing processes are used with fluorine-based etchants, then the wafer can be singulated into separate die, but the bond pads suffer from mechanical stress and increased resistance due to damage from the etchants

Engineering Contradiction:
Improvewafer singulation efficiencyVSAvoidbond pad resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A titanium contact layer is introduced as an intermediary between the aluminum-copper bond pad layer and the fluorine-based etchant environment. This titanium layer acts as a protective mediator that is resistant to fluorine-based etchants, preventing direct contact and damage to the bond pad metal while still allowing the etching process to proceed for wafer singulation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The titanium contact layer is deposited onto the bond pad structure before the wafer singulation process. This preliminary protective action ensures that when fluorine-based etchants are subsequently applied during dicing, the bond pad metal is already shielded, preventing damage before it can occur

Inventive Principle:
Principle #10Preliminary action

2Reliability

If aluminum-copper bond pad structures are used, then good electrical conductivity is achieved, but the bond pads are damaged by fluorine-based etchants causing increased resistance

Engineering Contradiction:
Improveelectrical conductivityVSAvoidetchant damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The titanium contact layer serves as a protective intermediary that is chemically resistant to fluorine-based etchants. It is deposited over the aluminum-copper bond pad structure, allowing the etching process to proceed while preventing the harmful etchant from directly contacting and damaging the conductive bond pad metal

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The bond pad structure is transformed into a composite multi-layer structure consisting of the aluminum-copper conductive layer combined with an outer titanium protective layer. This composite structure maintains the electrical conductivity benefits of aluminum-copper while adding the chemical resistance properties of titanium

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in bond pads with low resistance (less than 20 ohms), reducing power consumption and improving performance by preventing damage from fluorine-based etchants and minimizing the number of deposition processes, thus lowering costs.

Implementation Method 1

A method of forming integrated chip die with a bond pad structure that includes a titanium contact layer resistant to fluorine-based etchants, using a masking layer to protect the contact layer during etching and patterning

Methodology Applied
Scientific EffectSelective etching resistance:

Data Source

PatentUS20240387424A1Film structure for bond pad
Publication Date: 2024.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240387424A1 patent drawing
  • US20240387424A1 patent drawing
  • US20240387424A1 patent drawing

AI summary

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure over a substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A bond pad structure is over the interconnect structure, a first masking layer is over the bond pad structure, and a second masking layer is over the first masking layer. The second masking layer contacts opposing outermost sidewalls of the bond pad structure and the first masking layer. A conductive bump vertically extends through the first masking layer and the second masking layer to contact the bond pad structure.