Bond Pad Via Landing Layout for SoIC Thermal Reliability
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Solution Overview
Problem
The increasing complexity of integrated circuits in System on Integrated Chip (SoIC) packaging poses challenges in thermal reliability and silicon area utilization due to the large bond pad vias, which can lead to performance degradation and reliability issues.
Innovation Solution
The implementation of a specific design for bond pad via landing, including a keep-out zone, metal pad recess, and metal pad lateral recess, optimizes the bond pad via landing to enhance thermal reliability and reduce the occupied area of the top metal component, thereby improving the integration and performance of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large bond pad vias are used in SoIC packaging, then electrical connectivity between device dies is achieved, but thermal reliability deteriorates and silicon area utilization decreases
Solution Approach 1:
The bond pad via structure is segmented into multiple functional zones: a via region for electrical connectivity, a keep-out zone to prevent metal component interference, and recess regions (metal pad recess and lateral recess) to reduce thermal stress. This segmentation allows each zone to optimize its function, improving thermal reliability while minimizing silicon area consumption.
Solution Approach 2:
Different regions of the bond pad via structure are assigned different properties: the via region provides electrical conductivity, the keep-out zone provides thermal isolation, and the recess regions provide mechanical stress relief. This local differentiation of properties enables the structure to simultaneously achieve electrical connectivity and thermal reliability without excessive area occupation.
2Reliability
If large bond pad vias are used to ensure electrical connectivity, then device functionality is achieved, but top metal component area increases leading to performance degradation
Solution Approach 1:
The top metal component area is segmented by introducing a keep-out zone that prevents metal extension into critical regions. This segmentation isolates the electrical connectivity function to the via region while preventing metal components from occupying excessive area, thereby maintaining device reliability without increasing overall metal area.
Solution Approach 2:
The keep-out zone extracts or removes the metal component from the bond pad via region, preventing it from occupying space that would otherwise be used for reliable electrical connectivity. This extraction ensures that metal components do not interfere with the via structure, maintaining reliability while reducing top metal area.
3Ease of manufacture
If bond pad vias are formed without optimized landing design, then manufacturing is simpler, but thermal reliability and yield deteriorate
Solution Approach 1:
The keep-out zone and recess regions are defined in advance during the via formation process, establishing thermal and mechanical boundaries before subsequent manufacturing steps. This preliminary definition of zones ensures thermal reliability is built into the structure from the outset, preventing yield deterioration without significantly complicating the manufacturing process.
Data Source
AI summary
A method of fabricating a semiconductor device that includes a first die component and at least one second die component. The first die component includes a substrate, a dielectric layer on the substrate, and one or more metal pads positioned on the dielectric layer. The first die component further includes a passivation/bond film layer that is formed over the one or more metal pads, and one or more bond pad vias that extend through the passivation/bond film layer and contact one or more metal pads. The at least one second die component is bonded to the first die component and includes a substrate, and one or more through silicon vias, with the one or more through silicon vias contacting the one or more bond pad vias.