3D Bond Wire Inductor Layout for Compact Memory Boost Conversion
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Solution Overview
Problem
Traditional induction devices, such as spiral inductors, face size restrictions in memory devices, leading to reduced output voltage and inadequate inductance and Q-factor, making them unsuitable for on-chip, on-interposer, or on-board applications.
Innovation Solution
A bond wire induction apparatus and conductive node induction apparatus are used in conjunction, with the bond wire induction apparatus generating additional inductance outside the substrate and the conductive node induction apparatus providing high inductance and Q-factor within the substrate, forming a coreless induction system with parallel conductive nodes and bond traces to enhance inductance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional spiral inductors are used in memory devices, then the device structure is simple and easy to manufacture, but the inductance and Q-factor are insufficient and output voltage is reduced
Solution Approach 1:
The induction apparatus is divided into two separate components: a conductive node induction apparatus integrated within the substrate and a bond wire induction apparatus external to the substrate. This segmentation allows each component to be optimized independently, with the conductive nodes providing a foundation for inductance and the bond wires adding significant inductance value, thereby achieving high inductance and Q-factor while remaining manufacturable
Solution Approach 2:
The invention extends the induction system from a two-dimensional planar spiral inductor to a three-dimensional structure by utilizing bond wires that extend vertically from the substrate surface. This dimensional transition creates a larger effective loop area for the magnetic field, significantly increasing inductance without increasing the substrate footprint, thus resolving the contradiction between manufacturability and performance
2Area of stationary object
If the induction apparatus size is reduced for on-chip applications, then the device fits within size restrictions, but the inductance and output voltage are reduced
Solution Approach 1:
By transitioning from a planar 2D spiral inductor to a 3D structure utilizing vertical bond wires extending from the substrate, the invention achieves large inductance values within a compact footprint. The bond wires create extended magnetic loop areas perpendicular to the substrate plane, providing high inductance without increasing the substrate area
Solution Approach 2:
The conductive nodes are integrated within the substrate layers while the bond wires are attached to and extend from these nodes. This nested configuration allows the induction apparatus to be compactly integrated into the memory device structure while maintaining high inductance through the combined effect of the embedded nodes and external wires
3Power
If a DC/DC boost converter is used in memory devices, then voltage conversion is achieved, but the inductor size restrictions reduce output voltage and efficiency
Solution Approach 1:
The induction apparatus is segmented into conductive nodes within the substrate and bond wires external to it, allowing the inductance function to be distributed across different spatial locations. This enables the DC/DC boost converter to achieve required voltage conversion with a much smaller overall inductor footprint than traditional designs
Solution Approach 2:
The bond wire induction apparatus utilizes the vertical dimension by extending wires perpendicular to the substrate surface, creating large magnetic loop areas in three-dimensional space. This allows the DC/DC boost converter to achieve high output voltage and efficiency without being constrained by planar area restrictions on the substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased inductance and Q-factor within smaller form factors, effectively addressing the limitations of traditional induction devices by providing higher output voltage and improved efficiency in memory devices.
Implementation Method 1
the bond wire induction apparatus can generate a second induction. In these embodiments, the first induction and the second induction can be utilized with a DC/DC boost converter
Data Source
AI summary
Systems, methods, and apparatus are provided for a bond wire induction apparatus. A particular induction apparatus can include a memory package comprising a substrate and a plurality of memory layers, a plurality of conductive nodes connected by a plurality of conductive traces to form a first portion of an induction device. In this embodiment, the first portion of the inductive device comprises an inductive coil within at least two layers of the plurality of memory layers of the memory package. In addition, the apparatus can include a plurality of bond traces to couple a first portion of the plurality of conductive nodes to a second portion of the plurality of conductive nodes to form a second portion of the inductive device, such that the second portion of the inductive device comprises an inductive bond wire in a physical area that is physically outside the memory package.