Bonded 3D Memory Cell Arrays With Independent Bit Line Operation
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and reliability while maintaining efficient integration of memory cells.
Innovation Solution
A semiconductor memory device is designed with a first and second cell array structure, each comprising cell strings and memory cells connected to bit lines and common source lines, with direct bonding of bonding pads and word lines, allowing for perpendicular spacing and independent control of operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensionally arranged memory cells are used, then the device structure is simple, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple cell array structures vertically. Multiple cell strings are arranged in vertical layers with bonding pads from different layers directly bonded together, enabling increased storage capacity through vertical integration while maintaining manageable structural complexity through systematic layering and bonding approaches
2Quantity of substance
If memory cells are densely integrated, then the data storage capacity increases, but the reliability decreases
Solution Approach 1:
The memory device is divided into multiple independent cell array structures with separate bit lines and common source lines for each structure. This segmentation allows independent operation and control of each cell array, reducing interference between densely integrated memory cells while maintaining high storage capacity through vertical stacking and direct bonding of corresponding bonding pads between structures
Data Source
AI summary
A semiconductor memory device includes a first cell array structure including a plurality of first cell strings, a plurality of first bonding pads, a first bit line, and a first common source line, and a plurality of first word lines; and a second cell array structure including a plurality of second cell strings, a plurality of second bonding pads, a second bit line, a second common source line, and a plurality of second word lines, where the plurality of first bonding pads are bonded to the plurality of second bonding pads, where the plurality of first word lines are electrically connected to the plurality of second word lines, where the first bit line is electrically separated from the second bit line, and where the first common source line is electrically separated from the second common source line.