Bonded 3D Memory Assemblies for Higher Density Without Fine Scaling
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Solution Overview
Problem
Planar memory cells face density limitations as feature sizes approach a lower limit, making scaling and fabrication challenging and costly, while 3D memory architectures offer a solution to increase memory density.
Innovation Solution
A 3D memory device is constructed by bonding two semiconductor assemblies with an inter-assembly bonding layer, each assembly comprising a memory stack and peripheral circuits, allowing for increased cell density without sacrificing cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes to increase density, then memory density improves, but fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional stacked architecture. Multiple memory stacks are formed vertically on the substrate, with each stack containing multiple memory cells. This vertical stacking enables significant increase in memory density without reducing the lateral footprint or feature size, thereby avoiding the fabrication challenges associated with extreme scaling.
2Quantity of substance
If feature sizes are reduced to increase memory density, then storage capacity improves, but process technology becomes challenging and costly
Solution Approach 1:
Instead of reducing feature sizes laterally, the patent increases storage capacity by stacking multiple memory structures vertically. Each memory stack comprises alternating conductive and dielectric layers formed through conventional thin-film deposition processes, avoiding the need for advanced lithography and precise feature patterning at extremely small dimensions.
Solution Approach 2:
The memory device is divided into multiple discrete memory stacks, each stack being a self-contained unit with conductive layers and dielectric layers. This segmentation allows each stack to be formed using standard process technologies, and the overall storage capacity is increased by multiplying the number of stacks rather than by miniaturizing individual features.
3Quantity of substance
If multiple memory stacks are bonded together to increase density, then storage capacity doubles, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into separate stages: first, multiple memory stacks are formed on a single substrate; second, the substrate is divided into separate semiconductor assemblies, each containing one or more memory stacks; third, these assemblies are bonded together. This segmentation of the manufacturing process simplifies each individual step while achieving the overall goal of high-density storage.
Solution Approach 2:
The patent employs vertical stacking of memory structures in the third dimension, allowing multiple memory cells to occupy the same lateral footprint. This approach increases storage capacity without requiring proportional increases in lateral manufacturing complexity, as the vertical layers are formed through sequential deposition processes.
4Productivity
If conventional bonding methods are used to join semiconductor assemblies, then manufacturing time is long and thermal damage occurs
Solution Approach 1:
The patent replaces conventional thermal bonding methods with direct mechanical bonding. The semiconductor assemblies are brought into direct contact and bonded through applied pressure without requiring high temperatures. This mechanical bonding approach eliminates thermal damage to sensitive memory structures and reduces manufacturing time by eliminating thermal processing steps.
Data Source
AI summary
Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.