Bonded 3D Memory Structure With Isolated Dummy Source Line
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity, particularly in electronic systems that require efficient storage solutions, as existing methods do not effectively utilize three-dimensional memory cell arrangements and bonding structures to enhance storage capabilities.
Innovation Solution
A semiconductor device with a bonded structure comprising a first substrate with a peripheral circuit and insulating structure, and a second structure with a common source plate, cell stack, and insulating structure, where the cell stack includes gate electrodes and channel structures connected to the common source plate, and a dummy block is electrically isolated from the main blocks to reduce input-output capacitance and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory cell arrangement is implemented to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into two separate structures that are subsequently bonded together. The first structure contains peripheral circuits on a first substrate, while the second structure contains memory cell stacks on a second substrate. This segmentation allows independent optimization of each structure and simplifies the overall manufacturing process while achieving high storage capacity through vertical stacking.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cell stacks. Multiple memory cells are stacked in the vertical direction, with each stack containing multiple levels of bit lines, word lines, and memory elements, thereby dramatically increasing storage capacity within the same footprint.
2Quantity of substance
If bonding structures are used to combine separate substrate portions, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The memory device is divided into two separate structures that are subsequently bonded together. The first structure contains peripheral circuits on a first substrate, while the second structure contains memory cell stacks on a second substrate. This segmentation allows independent optimization of each structure and simplifies the overall manufacturing process while achieving high storage capacity through vertical stacking.
Solution Approach 2:
The first and second structures are prepared separately with their respective circuits and memory cells formed before bonding. Insulating structures and bonding pads are pre-formed on both substrates to facilitate subsequent bonding. This preliminary preparation simplifies the bonding process and enables mass production while maintaining high storage capacity.
3Ease of operation
If dummy blocks are added to the cell stack, then input-output performance is improved through reduced capacitance, but device area increases
Solution Approach 1:
Dummy blocks are strategically positioned at specific locations within the memory array, particularly near input-output regions. These dummy blocks have different characteristics (such as different capacitance values or connectivity) compared to regular memory blocks. This local modification optimizes the electrical characteristics and reduces input-output capacitance without requiring a complete redesign of the entire memory structure.
Data Source
AI summary
A semiconductor device includes: a first structure including a first substrate and a peripheral circuit disposed on the first substrate; and a second structure including a common source plate and a cell stack disposed on the common source plate and including a plurality of gate electrodes and channel structures, wherein the cell stack includes a plurality of cell blocks including a plurality of main blocks and at least one dummy block disposed at one side of the plurality of main blocks, wherein the common source plate includes a main common source line region and a dummy common source line region, wherein the main common source line region overlaps the plurality of main blocks, and the dummy common source line region is separated from the main common source line region and overlaps the at least one dummy block by being electrically isolated from the at least one dummy block.