Bonded 3D Memory Stack Structure for Dense Cell Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and improving integration and electrical characteristics while maintaining productivity.
Innovation Solution
A semiconductor device design featuring a vertically-integrated structure with a stack of gate electrodes and channel structures, including a plate layer, channel layers, and separation regions, which allows for enhanced integration and electrical connectivity through bonding pads and interconnection structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking, where multiple memory cell layers are vertically stacked above each other. This dimensional change allows significantly increased storage capacity within the same footprint area, addressing the contradiction by utilizing vertical space to pack more storage elements without proportionally increasing overall device complexity.
Solution Approach 2:
The patent implements nested structures where channel structures are positioned within or alongside gate electrode structures, and multiple functional layers are integrated within each other. The separation regions are embedded within the stack structure, creating a compact nested arrangement that increases storage density while managing structural complexity through organized integration.
2Productivity
If vertically-integrated stack structure is implemented to improve integration, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into discrete modular layers including gate electrodes, interlayer insulating layers, channel structures, and separation regions. Each layer can be fabricated and positioned independently, allowing for modular assembly and reducing the cumulative precision requirements compared to forming all structures in a single complex process. This segmentation enables better control over manufacturing tolerances.
Solution Approach 2:
The patent introduces interlayer insulating layers as intermediary structures between conductive elements. These insulating layers provide spacing, electrical isolation, and mechanical support, facilitating the assembly of vertically-stacked components with relaxed precision requirements. The intermediary layers act as buffers that accommodate minor dimensional variations while maintaining functional integrity.
3Quantity of substance
If dense packing of memory cells is achieved to increase storage capacity, then storage capacity is improved, but electrical characteristics may deteriorate
Solution Approach 1:
The patent uses interlayer insulating layers and core insulating layers as intermediary structures that provide electrical isolation between adjacent conductive elements. These insulating layers prevent unwanted electrical coupling and interference, maintaining signal integrity even when memory cells are densely packed. The intermediaries ensure that increased density does not compromise electrical characteristics.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the device. Insulating layers are strategically placed in specific locations where electrical isolation is critical, while conductive channel structures are positioned where charge transport is needed. This localized optimization of material properties ensures that dense packing maintains good electrical characteristics by providing isolation where needed and conductivity where required.
Data Source
AI summary
A semiconductor device includes a first structure and a second structure thereon. The first structure includes a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure. The second structure includes a stack structure including: gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction; a plate layer that extends on the stack structure; channel structures within the stack structure, separation regions, which penetrate at least partially through the stack structure, and upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads.