Bonded 3D Memory Logic Die Segmentation
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Solution Overview
Problem
The degradation of CMOS devices due to collateral thermal cycling and hydrogen diffusion during the manufacture of three-dimensional memory devices poses challenges for the performance of support circuitry in bonded three-dimensional memory devices.
Innovation Solution
A semiconductor structure is formed with a memory die bonded to a logic die, featuring an alternating stack of insulating and conductive layers, memory stack structures with vertical semiconductor channels and memory films, a source layer connected to the end portions of the semiconductor channels, and a pass-through via structure extending through a dielectric material portion, allowing for improved support circuitry and reduced process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS devices are formed on the same substrate as three-dimensional memory devices, then support circuitry can be provided for write, read, and erase operations, but the CMOS devices degrade due to collateral thermal cycling and hydrogen diffusion
Solution Approach 1:
The patent separates the memory die from the logic die, with each formed on its own substrate. The memory die contains the three-dimensional memory cells while the logic die contains the CMOS support circuitry. This segmentation allows independent optimization and processing of each die, preventing thermal cycling and hydrogen diffusion from degrading the CMOS devices while maintaining full support circuitry functionality.
Solution Approach 2:
The patent introduces a bonding interface between separate memory and logic dies as an intermediary solution. This bonding structure enables electrical connection and signal transmission between the memory cells and support circuitry without requiring co-location on the same substrate, thereby isolating the CMOS devices from harmful thermal and chemical effects during memory device manufacturing.
2Ease of manufacture
If carrier substrate is removed to expose distal ends of vertical semiconductor channels, then source layer can be formed directly on channels, but process complexity increases
Solution Approach 1:
The carrier substrate is removed at an earlier stage in the manufacturing process, before source layer formation. This preliminary action exposes the distal ends of the vertical semiconductor channels in advance, allowing the source layer to be deposited directly onto the channels without requiring complex in-situ exposure techniques. The removed carrier substrate is replaced with a temporary support structure that maintains mechanical integrity during subsequent processing.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.