Bonded 3D Memory Logic Die Segmentation
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Solution Overview
Problem
The degradation of CMOS devices due to collateral thermal cycling and hydrogen diffusion during the manufacture of three-dimensional memory devices poses challenges for the performance of support circuitry in bonded three-dimensional memory devices, limiting the effectiveness of existing technologies.
Innovation Solution
The implementation of a semiconductor structure where a memory die is bonded to a logic die, featuring an alternating stack of insulating and electrically conductive layers, with a source layer connected to vertical semiconductor channels and backside bonding pads, allowing for high-performance support circuitry and easier implementation compared to conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS devices are formed on the same substrate as three-dimensional memory devices, then support circuitry can be provided, but performance is degraded due to collateral thermal cycling and hydrogen diffusion
Solution Approach 1:
The invention separates the memory die from the logic die, placing them on different substrates. The memory die is formed on a first substrate while the logic die (containing support circuitry) is formed on a second substrate, then the two dies are bonded together. This segmentation prevents the harmful thermal cycling and hydrogen diffusion that would occur if both were on the same substrate, while still providing the needed support circuitry functionality.
Solution Approach 2:
The invention introduces a bonding interface between separate memory and logic dies as an intermediary solution. This bonding structure allows the memory die and logic die to be electrically connected while physically separated, enabling support circuitry to function without being subjected to the harmful effects of collateral thermal cycling and hydrogen diffusion that would affect integrated CMOS devices on the same substrate.
2Ease of manufacture
If conventional methods are used to form bonded three-dimensional memory devices, then manufacturing can proceed, but the process is complex and performance is limited
Solution Approach 1:
The manufacturing process is segmented into distinct steps: forming the memory die on a first substrate, forming the logic die on a second substrate, and then bonding the two dies together. This segmentation allows each die to be optimized independently and simplifies the overall manufacturing process while avoiding the performance limitations of conventional integrated approaches.
Solution Approach 2:
The invention performs preliminary actions by forming the memory die and logic die separately on their respective substrates before bonding. This preliminary separation allows for independent optimization and simplification of each die's manufacturing process, making the overall fabrication easier while improving support circuitry performance by isolating it from harmful effects.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.