Bonded 3D Memory and Logic Dies for High-Temperature Isolation
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Solution Overview
Problem
As three-dimensional memory devices scale to smaller dimensions, the high temperature processing steps required for manufacturing adversely impact peripheral logic devices, necessitating a solution to protect these devices from such processing while maintaining high performance.
Innovation Solution
A semiconductor structure is formed with a three-dimensional memory device bonded to a peripheral logic die, where the logic devices are separated from high temperature processing steps by being bonded to a separate die, allowing them to operate at higher voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature processing steps are used for manufacturing three-dimensional memory devices, then memory device performance is improved, but peripheral logic devices are damaged
Solution Approach 1:
The device is divided into two separate dies: a first die containing the three-dimensional memory device and a second die containing the peripheral logic circuitry. This segmentation allows the memory die to undergo high temperature processing while the logic die is protected from thermal damage.
Solution Approach 2:
A bonded interface between the memory die and logic die acts as an intermediary, allowing electrical connection while physically separating the components. This enables the memory device to be processed at high temperatures without exposing the logic devices to damaging conditions.
2Device complexity
If peripheral logic devices are integrated on the same substrate as memory elements, then device complexity is reduced, but logic devices are exposed to high temperature processing
Solution Approach 1:
The integrated device is segmented into two separate dies that are subsequently bonded together. The first die contains memory elements and can withstand high temperature processing, while the second die contains logic devices that are sensitive to temperature. This segmentation resolves the contradiction by allowing physical separation while maintaining functional integration.
Solution Approach 2:
Instead of integrating logic devices on the same planar substrate as memory elements, the solution moves to a three-dimensional stacked architecture where the logic die is placed vertically above or beside the memory die and bonded through copper pads. This dimensional transition protects logic devices from high temperature exposure while maintaining electrical connectivity.
3Object-affected harmful factors
If logic devices are separated from memory elements by bonding to a separate die, then protection from high temperature processing is achieved, but device complexity increases
Solution Approach 1:
The separate memory die and logic die are merged into a single bonded assembly through copper pad bonding. This merging maintains electrical connectivity and functional integration while protecting logic devices from high temperature processing. The complexity increase is minimized by using standard bonding techniques and maintaining a relatively simple stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration protects the logic devices from adverse effects of high temperature processing, ensuring high performance and functionality of the three-dimensional memory device.
Implementation Method 1
bonding the first copper pads with the second copper pads through copper interdiffusion to provide multiple bonded pairs of a respective first copper pad and a respective second copper pad at an interface between the first die and the second die
Data Source
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AI summary
A first die includes a three-dimensional memory device and first copper pads. A second die includes a peripheral logic circuitry containing CMOS devices located on the semiconductor substrate and second copper pads. A bonded assembly is formed by bonding the first copper pads with the second copper pads through copper interdiffusion to provide multiple bonded pairs of a respective first copper pad and a respective second copper pad at an interface between the first die and the second die.