Bonded 3D Memory Device Isolating Support Circuitry
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Solution Overview
Problem
Three-dimensional memory devices face challenges in maintaining the performance of support circuitry due to degradation from collateral thermal cycling and hydrogen diffusion during the manufacturing of three-dimensional memory devices, which affects the reliability and efficiency of the memory arrays.
Innovation Solution
A bonded structure is formed by incorporating high-performance support circuitry on a different substrate than the three-dimensional memory array, followed by bonding the substrates together, allowing for independent optimization of both components and enhancing the overall performance of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If support circuitry is integrated on the same substrate as the three-dimensional memory array, then device complexity is reduced and manufacturing is simplified, but the support circuitry performance degrades due to thermal cycling and hydrogen diffusion
Solution Approach 1:
The device is divided into two separate substrates: a first substrate containing the three-dimensional memory array and a second substrate containing the support circuitry. This segmentation allows each substrate to be optimized independently for its specific function, preventing the support circuitry from experiencing degradation due to thermal cycling and hydrogen diffusion that occurs during memory array manufacturing.
Solution Approach 2:
A bonding interface is introduced as an intermediary between the first substrate (memory array) and the second substrate (support circuitry). This bonding interface enables electrical connection and mechanical support while physically isolating the support circuitry from the harsh manufacturing environment of the memory array, thus maintaining support circuitry performance.
2Reliability
If support circuitry is separated onto a different substrate, then reliability and performance are improved by isolating from degradation, but device complexity and manufacturing difficulty increase
Solution Approach 1:
By segmenting the device into separate substrates for memory and support circuitry, each can be manufactured and optimized independently using standard processes, then combined through bonding. This approach manages complexity by allowing parallel development and manufacturing of the two substrates.
Solution Approach 2:
The bonding interface serves multiple functions: it provides mechanical support, establishes electrical connections between substrates, and acts as a barrier to hydrogen diffusion. This multi-functionality reduces the need for additional components and simplifies the overall bonded structure.
3Ease of manufacture
If support circuitry is integrated on the same substrate, then manufacturing process is simplified, but thermal management becomes difficult and hydrogen diffusion affects performance
Solution Approach 1:
Separating the support circuitry onto a different substrate allows for independent thermal management of each substrate. The memory array substrate can be optimized for high-temperature processing while the support circuitry substrate can be designed with appropriate thermal pathways and heat dissipation structures, resolving the thermal management challenge.
Solution Approach 2:
The bonding interface acts as a thermal management intermediary, allowing for controlled thermal pathways between substrates. Different bonding methods and materials can be selected to optimize heat transfer or thermal isolation based on the specific thermal management requirements of each substrate.
Data Source
AI summary
A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.