Bonded 3D Memory Arrays With Thinned Substrates and Tight Via Pitch
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Solution Overview
Problem
Conventional memory arrays face challenges in increasing memory density due to limitations in the number of front-end of line (FEOL) transistors that can be formed on a semiconductor substrate, leading to increased complexity and cost when attempting to decrease critical dimensions of memory cells.
Innovation Solution
The implementation of vertically stacked and bonded memory arrays, where multiple layers of DRAM are separately fabricated on thinned semiconductor substrates and then sequentially stacked and bonded using a low-temperature bonding material, allowing for a tighter via pitch and increased memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If FEOL transistors are used on the upper-most layer of the semiconductor substrate, then memory cells can be formed, but memory density cannot be increased without decreasing critical dimensions which increases complexity and cost
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to vertically stacked (3D) memory arrays. Multiple memory layers are stacked in the vertical direction, with each layer containing memory cells formed by the intersection of word lines and bit lines. This dimensional change allows significant increase in memory density without reducing critical dimensions of individual cells, thereby avoiding increased process complexity and cost.
2Quantity of substance
If additional memory layers are processed on top of lower level memory cells, then memory density increases, but the lower level memory cells are damaged
Solution Approach 1:
The patent divides the memory device into multiple separately fabricated memory layers, each processed independently on its own substrate. The layers are then bonded together through intermediate bonding layers. This segmentation allows each layer to be manufactured and tested separately, preventing damage to lower level cells during processing of upper layers, while still achieving high memory density through vertical stacking.
3Quantity of substance
If memory arrays are formed over thick support structures, then substrate strength is maintained, but footprint area cannot be reduced for high density
Solution Approach 1:
The patent utilizes the vertical dimension to increase memory capacity while maintaining a compact footprint. By stacking multiple memory layers vertically and bonding them together, the device achieves high memory density without proportionally increasing the planar footprint area. The thick support structures are distributed across multiple thinner bonded layers, maintaining structural integrity while enabling high-density 3D architecture.
Data Source
AI summary
Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.