Bonded 3D NAND Memory Structure With Relaxed Alignment
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Solution Overview
Problem
Current 3D NAND memory devices face challenges in scaling due to difficulties in aligning and bonding high aspect ratio structures, leading to impaired product yield and limited carrier transport rates, which affect memory cell programming and erasure efficiency.
Innovation Solution
The proposed solution involves bonding semiconductor structures in a face-to-face manner with conductive routings extending to a bonding interface, allowing for conductive connection without direct alignment, and integrating peripheral circuits into a separate semiconductor structure, reducing alignment precision requirements and optimizing bonding contact layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If direct alignment bonding of high aspect ratio structures is used, then bonding precision is improved, but manufacturing complexity and difficulty increase significantly
Solution Approach 1:
The patent introduces bonding pads as intermediary elements that extend conductive routings to the bonding interface. These bonding pads serve as mediators between the high aspect ratio structures, allowing face-to-face bonding without requiring direct alignment of the complex structures themselves. The bonding pads simplify the bonding process by providing flat, accessible bonding surfaces while maintaining electrical connectivity through the extended routings.
2Reliability
If bonding contact layout is optimized, then carrier transport rate is improved, but alignment precision requirements increase
Solution Approach 1:
The patent extends conductive routings from the high aspect ratio structures to the bonding interface in the lateral dimension. This dimensional extension allows the bonding contacts to be positioned optimally for carrier transport while maintaining electrical connectivity through the extended routings. The bonding pads are positioned at the bonding interface plane, separating the optimal bonding contact layout from the structural alignment requirements.
3Volume of moving object
If peripheral circuits are integrated into separate semiconductor structure, then chip size is reduced, but device complexity increases
Solution Approach 1:
The patent divides the memory device into separate semiconductor structures: one containing the memory array and another containing the peripheral circuits. This segmentation allows each structure to be optimized independently and bonded together through the bonding interface. The face-to-face bonding of segmented structures achieves compact integration while maintaining functional separation, reducing overall chip size despite the increased architectural complexity.
Data Source
AI summary
Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.