Bonded 3D NAND Memory With Orientation-Optimized Logic Die
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Solution Overview
Problem
The performance of support circuitry in three-dimensional NAND memory devices is limited by the crystallographic orientations of the substrate, and mechanical stress from vertical NAND strings affects the reliability of these devices.
Innovation Solution
A bonded structure is created using a performance-optimized support chip and stress-optimized three-dimensional memory chips with different crystallographic orientations for die directions, involving a memory die with a three-dimensional memory array on a single crystalline semiconductor substrate and a logic die with field effect transistors on another substrate, where the crystallographic orientations are specifically aligned to minimize adverse mechanical stress and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single crystallographic orientation is used for the substrate, then the manufacturing process is simplified, but the mechanical stress from vertical NAND strings degrades device reliability
Solution Approach 1:
The substrate is segmented into two separate dies with different crystallographic orientations. The first die uses a first crystallographic orientation optimized for memory array performance, while the second die uses a second crystallographic orientation optimized for support circuitry performance. This segmentation allows each die to be independently optimized for its specific function, resolving the contradiction between manufacturing simplicity and device reliability by eliminating mechanical stress through orientation differentiation.
Solution Approach 2:
Different regions of the bonded structure are assigned different crystallographic orientations based on their specific functional requirements. The memory array region uses one orientation optimized for vertical NAND string performance, while the support circuitry region uses another orientation optimized for transistor performance. This local quality approach ensures that each region experiences minimal mechanical stress for its specific function, thereby improving overall device reliability.
2Reliability
If different crystallographic orientations are used for support chip and memory chips, then mechanical stress is minimized and performance is enhanced, but the device complexity increases
Solution Approach 1:
Two separately fabricated dies with different crystallographic orientations are merged through a bonding process to form a single integrated device. The first die containing the memory array and the second die containing the support circuitry are bonded together using known techniques such as eutectic bonding, copper-copper bonding, or die-to-wafer bonding. This merging approach manages device complexity by using established bonding processes while achieving the benefits of different crystallographic orientations for improved reliability and performance.
3Power
If the channel direction of logic die is aligned with word lines or bit lines, then electrical performance is optimized, but the crystallographic orientation alignment becomes more constrained
Solution Approach 1:
The bonding process incorporates rotational degrees of freedom that allow dynamic adjustment of the logic die orientation relative to the memory die. By enabling rotation during bonding, the system can optimize the channel direction alignment with respect to word lines or bit lines based on electrical performance requirements, while managing orientation alignment constraints through flexible positioning rather than fixed constraints.
Data Source
AI summary
A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.