Bonded Semiconductor Assembly With Sacrificial Spacer Release

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Solution Overview

Problem

The existing semiconductor device manufacturing processes face challenges in efficiently forming bonded assemblies and recycling substrates without the need for costly grinding processes that can stress semiconductor devices.

Innovation Solution

A method involving the formation of an etch stop material layer, a planar sacrificial spacer layer, and an insulating encapsulation layer on a first substrate, followed by bonding with second semiconductor devices on a second substrate, and then selectively removing the sacrificial spacer layer using a wet etch process to detach the first substrate from the assembly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If substrate thinning by grinding is performed before dicing, then electrical contacts can be formed, but process costs increase and semiconductor devices are stressed

Engineering Contradiction:
Improveelectrical contact formationVSAvoidprocess cost
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent extracts the substrate thinning operation from the manufacturing process by using wafer bonding to achieve electrical contacts without grinding. The bonded assembly allows contacts to be formed through the bond interface itself, eliminating the need for mechanical removal of substrate material and thereby reducing process costs and device stress.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a bonding interface as an intermediary between substrates to enable electrical contact formation. By bonding two substrates together with semiconductor devices facing each other, the bond interface serves as the contact pathway, replacing the traditional grinding-based contact formation method.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If substrate thinning by grinding is performed, then electrical contacts can be formed, but semiconductor devices experience stress

Engineering Contradiction:
Improveelectrical contact formationVSAvoiddevice stress
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent removes the mechanical stress-inducing grinding step from the process. By forming electrical contacts through the wafer bonding interface rather than through mechanical thinning, the method eliminates the source of device stress while maintaining the ability to form functional electrical contacts.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The bonding interface acts as a stress-free intermediary for electrical contact formation. Instead of mechanically thinning substrates which induces stress, the patent uses the bonded interface between substrates as the contact pathway, preserving device integrity and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If substrates are used for bonding, then bonded assemblies can be formed, but substrates cannot be reused

Engineering Contradiction:
Improvebonded assembly formationVSAvoidsubstrate consumption
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

The patent recovers substrates for reuse after bonded assembly formation. By designing the process so that substrates can be detached from the bonded assembly after the devices are transferred, the method enables substrate recycling and reduces material consumption while maintaining high productivity in bonded assembly production.

Inventive Principle:
Principle #34Discarding and recovering

Solution Approach 2:

The patent performs preliminary substrate preparation including forming etch stop layers and sacrificial spacer layers that enable subsequent substrate detachment and reuse. These preliminary structures are designed to facilitate the recovery and recycling of substrates after they have served their bonding function.

Inventive Principle:
Principle #10Preliminary action

4Productivity

If traditional bonding processes are used, then assembled devices can be formed, but the process is complex and costly

Engineering Contradiction:
Improveassembled device formationVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the bonding process into distinct functional layers including etch stop layers, sacrificial spacer layers, and device layers. This segmentation allows for simplified, modular processing steps that reduce overall process complexity while maintaining high productivity in assembled device formation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary formation of etch stop layers and sacrificial spacer layers that simplify subsequent processing steps. These preliminary structures enable easier device transfer and substrate detachment, reducing the complexity of the overall bonding process while maintaining efficient assembled device production.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces process costs by eliminating substrate thinning through grinding and allows for the reuse of substrates, thereby minimizing material consumption and stress on semiconductor devices.

Implementation Method 1

removing the planar sacrificial spacer layer selective to the etch stop material layer and the insulating encapsulation layer by performing a wet etch process in which an isotropic etchant is introduced into the inter-die trenches

Methodology Applied
Scientific EffectWet etch process: Chemical Bonding

Data Source

PatentUS12288719B2Semiconductor device manufacturing process including forming a bonded assembly and substrate recycling
Publication Date: 2025.04.29 SANDISK TECHNOLOGIES LLC
  • US12288719B2 patent drawing
  • US12288719B2 patent drawing
  • US12288719B2 patent drawing

AI summary

A method includes forming an etch stop material layer and a planar sacrificial spacer layer over a front surface of a first substrate, forming an insulating encapsulation layer over the planar sacrificial spacer layer and on a backside surface and a side surface of the first substrate, forming a continuous structure including first semiconductor devices over a top surface of the insulating encapsulation layer, etching inter-die trenches within the continuous structure to divide the continuous structure, bonding the divided continuous structure to second semiconductor devices located over a second substrate, selectively removing the planar sacrificial spacer layer by performing a wet etch process in which an isotropic etchant is introduced into the inter-die trenches, and detaching the first substrate from an assembly of the second substrate, the second semiconductor devices, and the divided continuous structure after the removing the planar sacrificial spacer layer.