Molecularly Bonded Capacitor Chip Integration for Low-ESL Power Delivery
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Solution Overview
Problem
Conventional methods for connecting capacitors to electronic circuits result in significant equivalent stray inductances and resistances, limiting the efficiency of power supply to sensitive electronic devices, which requires high-density, low-ESL and ESR connections close to transistors.
Innovation Solution
The use of molecular bonding between a chip with an electronic circuit and a high-density capacitor chip, where the capacitor features a stack of insulating and conductive layers in an anodized metal region, allowing for very close integration and high connection density via hybrid or oxide-to-oxide bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional wire connection or metal ball connection is used to connect capacitors to electronic circuits, then the connection method is simple and easy to manufacture, but the equivalent stray inductances and resistances are significant, limiting power supply efficiency
Solution Approach 1:
The patent merges the capacitor chip and the electronic circuit chip into a single integrated unit through direct bonding. The capacitor chip is bonded directly to the same substrate as the electronic circuit, eliminating the need for separate connection elements like wires or metal balls. This integration reduces the physical distance and number of interfaces between the capacitor and the circuit, thereby minimizing stray inductances and resistances while improving power supply efficiency.
2Loss of energy
If capacitors are placed close to electronic circuits to optimize power supply, then power supply efficiency is improved, but the manufacturing precision and bonding complexity increase significantly
Solution Approach 1:
The patent segments the system into two separate chips (electronic circuit chip and capacitor chip) that are manufactured independently and then bonded together. This segmentation allows each chip to be optimized and manufactured separately with standard precision requirements, while the bonding process uses alignment features and controlled conditions to achieve the necessary precision. This approach avoids the need for extremely high precision in a single monolithic structure.
Solution Approach 2:
The patent introduces an intermediary bonding layer or bonding process that facilitates the connection between the capacitor chip and the electronic circuit chip. This intermediary bonding mechanism provides tolerance for alignment variations and reduces the stringency of precision requirements, while still achieving the goal of placing the capacitor close to the circuit for optimized power supply.
3Productivity
If high-density capacitor integration is implemented, then connection density is increased, but the manufacturing process complexity and difficulty increase
Solution Approach 1:
The patent performs preliminary actions by pre-configuring the capacitor chip with appropriate connection structures and bonding surfaces before the final bonding process. The capacitor chip is manufactured with predefined connection terminals and bonding layers that facilitate high-density integration. This preliminary preparation simplifies the subsequent bonding process and enables high connection density without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces equivalent stray inductances and resistances, enhancing the efficiency of power supply to sensitive electronic devices by enabling very high connection densities and minimizing interference.
Implementation Method 1
a capacitor comprising a stack of a first insulating layer between two second conductive layers, the stack being located in a first anodized metal region
Implementation Method 2
the anodizing of the metal layer at the locations of the first and second regions
Implementation Method 3
the first and second chips are bonded by hybrid molecular bonding, the third insulating layer and the interconnection network comprising first conductive tracks located in contact with one another
Data Source
AI summary
A device including first and second chips, the first chip including an electronic circuit and the second chip including a capacitor having a density greater than 700 nF/mm{circumflex over ( )}2, the first and second chips being bonded to each other by molecular bonding.