Bonded Deep Trench Capacitor Die for Logic Power Integrity
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Solution Overview
Problem
High-performance logic circuits require high-density capacitors to reduce simultaneous switching noise and voltage drop, but existing capacitors have low density, failing to meet the power integrity requirements of high-performance packages.
Innovation Solution
A package with deep partition capacitors is formed, where a high-density deep trench capacitor is integrated into a separate capacitor die and bonded directly to the lower redistribution layers of a logic die, allowing short electrical paths to devices and achieving high capacitance density without interfering with the logic die design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitors are used in high-performance logic circuits, then the device complexity is low and manufacturing is easier, but the capacitor density is insufficient to reduce simultaneous switching noise and voltage drop
Solution Approach 1:
The package is segmented into distinct functional components: a logic die and a separate capacitor die. The capacitor die is dedicated solely to housing high-density capacitors, while the logic die focuses on logic circuit functionality. This segmentation allows the capacitor density to be maximized in the capacitor die without compromising the logic die design, thereby achieving high capacitor density while maintaining manageable device complexity through functional specialization.
Solution Approach 2:
The capacitors are arranged in a three-dimensional deep trench structure within the capacitor die, utilizing vertical space rather than only planar area. This dimensional approach allows significantly higher capacitor density by stacking capacitor elements vertically into the substrate, transforming the traditional two-dimensional capacitor layout into a three-dimensional configuration that maximizes capacitance per unit area.
2Reliability
If capacitor density is increased to reduce simultaneous switching noise and voltage drop, then power integrity improves, but the electrical path length and interference with logic die design increase
Solution Approach 1:
The capacitor die and logic die are merged into a single integrated package structure with direct bonding between the two dies. The capacitors in the capacitor die are electrically connected to the logic circuits through short inter-die bonding paths, combining the benefits of high capacitor density with minimal electrical path length. This integration ensures that the high-density capacitors can effectively reduce simultaneous switching noise and voltage drop without introducing excessive path length delays.
3Quantity of substance
If high-density deep trench capacitors are integrated into a separate capacitor die, then capacitor density increases significantly, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into separate fabrication flows for the logic die and capacitor die, allowing each to be optimized independently. The capacitor die can be manufactured with deep trench capacitor structures using specialized processes, while the logic die follows standard logic fabrication. The two are then bonded together, simplifying the overall manufacturing by avoiding the need to integrate complex deep trench structures into every logic die.
Solution Approach 2:
The separate capacitor die acts as an intermediary component that bridges the power delivery requirements and the logic circuits. This intermediary approach allows the complex deep trench capacitor structures to be isolated in a dedicated die, which then interfaces with the logic die through standard bonding techniques, reducing the manufacturing complexity of the overall system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves very high capacitor density, reducing electrical paths and enhancing power integrity by utilizing high-density capacitors effectively within the power-delivery network of logic dies, such as CPUs and GPUs.
Implementation Method 1
a capacitor electrically coupled to the second plurality of bond pads
Data Source
AI summary
A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.