Bonded C-FET Wafer Stack to Reduce Lattice Mismatch
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Solution Overview
Problem
The semiconductor industry faces challenges in forming complementary field effect transistors (C-FETs) with stacked multi-gate devices, particularly due to lattice mismatch issues and high thermal budgets associated with alternating stacks of semiconductor layers, which can lead to defects and reduced quality of the device.
Innovation Solution
A method is described to form a C-FET structure using a composite stack formed from two half-stacks bonded together, where each stack is epitaxially grown separately, reducing the need for a middle layer with different composition and minimizing lattice mismatch, and direct bonding of bonding layers eliminates the need for additional semiconductor layers, thereby improving the quality of the composite stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If alternating stacks of semiconductor layers are used to form C-FET structures, then device density and performance are improved, but lattice mismatch issues and thermal budget-related defects increase
Solution Approach 1:
The patent divides the C-FET structure formation into two separate half-stack epitaxial growth processes instead of one alternating stack. Each half-stack is grown independently on separate substrates, then bonded together. This segmentation eliminates the need for alternating layer deposition, reducing lattice mismatch issues and thermal budget-related defects while maintaining high device density.
Solution Approach 2:
The patent performs preliminary epitaxial growth of complete half-stacks on separate substrates before bonding them together. This preliminary action allows each half-stack to be optimized independently and reduces the complexity of forming alternating stacks, thereby improving device quality while achieving the desired alternating n-type and p-type structure.
2Stability of the object's composition
If a middle layer with different composition is used to join stacks, then structural continuity is achieved, but lattice mismatch and defect formation increase
Solution Approach 1:
The patent removes the middle layer with different composition from the structure entirely. Instead of inserting an intermediate layer to join the stacks, the method directly bonds the epitaxially grown layers from opposite sides of the wafer, eliminating the source of lattice mismatch and defect formation while maintaining structural continuity through direct bonding.
Solution Approach 2:
The patent uses wafer bonding to create a mirror-image structure where the second half-stack is bonded to the first half-stack in reverse orientation. This copying approach allows symmetric structures to be formed without requiring intermediate layers, reducing lattice mismatch while achieving structural continuity.
3Ease of manufacture
If additional semiconductor layers are added to facilitate bonding, then bonding feasibility is improved, but device complexity and defect risk increase
Solution Approach 1:
The patent merges the bonding process with the existing epitaxial growth process. The same epitaxial growth process used to form the semiconductor layers is also used to form the bonding layers, eliminating the need for separate additional layers. This merging reduces device complexity while maintaining bonding feasibility through direct epitaxial bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of the C-FET structure by reducing lattice mismatch and thermal budget-related defects, leading to improved performance and reliability of the semiconductor device.
Implementation Method 1
direct bonding of bonding layers eliminates the need for additional semiconductor layers
Implementation Method 2
each stack is epitaxially grown separately
Data Source
AI summary
Semiconductor structures and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first bottom source/drain feature and a second bottom source/drain feature disposed over a substrate, a plurality of bottom channel members extending between and in contact with the first bottom source/drain feature and the second bottom source/drain feature, a first bonding layer over the plurality of bottom channel members, a second bonding layer disposed directly on the first bonding layer, a first top source/drain feature disposed directly over the first bottom source/drain feature, a second top source/drain feature disposed directly over the second bottom source/drain feature, and a plurality of top channel members disposed over the second bonding layer and extending between and in contact with the first top source/drain feature and the second top source/drain feature.