Bonded Unified Semiconductor Chip for Fast Processor-Memory Transfer
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Solution Overview
Problem
In modern mobile devices, the separate placement of application processors and memory (DRAM and NAND) on the PCB leads to low data throughput and increased PCB size, limiting battery capacity and device compactness due to long interlinks and the need for on-chip memory in processors.
Innovation Solution
A unified semiconductor chip integrating processors, embedded DRAM, and NAND memory on the same substrate with a bonding interface for direct, high-speed data transfer, reducing the need for on-chip memory and minimizing PCB space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processors and memory are placed separately on the PCB, then device functionality is achieved, but data transfer speed is low and PCB size is increased
Solution Approach 1:
The patent combines processors and memory (DRAM and NAND) into a single unified semiconductor chip, eliminating the need for separate PCB placement. This integration directly addresses the contradiction by enabling high-speed data transfer between components while minimizing PCB footprint, as all components communicate through short on-chip interconnects rather than long PCB traces
2Use of energy by moving object
If processors and memory are placed separately on the PCB, then device functionality is achieved, but interlink length is increased leading to higher power consumption
Solution Approach 1:
By integrating processors and memory on the same chip substrate, the patent dramatically reduces interlink length from PCB-level distances to micrometer-scale on-chip connections. This reduction directly lowers power consumption associated with data transmission, resolving the contradiction between energy efficiency and functional connectivity
3Speed
If on-chip memory is included in processors to compensate for slow external memory access, then data access speed is improved, but chip size and cost are increased
Solution Approach 1:
The patent transitions from a two-dimensional PCB layout to a three-dimensional stacked architecture, placing memory layers above and below the processor layer. This vertical integration enables high-capacity memory with fast access speeds while maintaining a compact chip footprint, resolving the contradiction between data access speed and chip area
Solution Approach 2:
The unified chip architecture merges processors with high-capacity DRAM and NAND memory in a single integrated structure. This combination eliminates the need for separate on-chip cache memory in processors, as the integrated memory provides sufficient buffering capacity, thereby reducing overall chip size while maintaining fast data access
Data Source
Figure 1A~1B
Figure 2
Figure 3A
AI summary
Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a unified semiconductor chip includes a first semiconductor structure including one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. The unified semiconductor chip also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The unified semiconductor chip further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.