Bonded Control Circuitry Over Memory Arrays for Faster Memory Access
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Solution Overview
Problem
Existing microelectronic device designs face challenges in reducing feature size and improving performance due to the presence of control logic devices that impede size reduction and performance enhancements, such as faster memory cell switching and lower power consumption.
Innovation Solution
A microelectronic device design featuring a control circuitry structure vertically overlying and bonded to a memory array structure, with sense amplifiers and sub-word line drivers positioned diagonally and horizontally overlapping memory array regions, allowing for a 'CMOS above array' configuration that reduces interference and enhances performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are placed within a base control logic structure underlying the memory array, then the memory device can be controlled, but the horizontal footprint size increases and performance is degraded
Solution Approach 1:
The patent transitions control logic devices from a planar configuration (underlying the memory array in the same horizontal plane) to a vertical configuration (overlying the memory array in a different horizontal plane). This dimensional change allows control logic to be stacked above the memory array, reducing the horizontal footprint while maintaining control functionality through vertical interconnect structures.
Solution Approach 2:
The patent segments the device into distinct horizontal planes: the memory array structure in a first horizontal plane and the control logic structure in a second horizontal plane. This segmentation enables independent optimization of each layer and facilitates vertical integration, reducing the overall horizontal footprint while preserving control functions.
2Reliability
If control logic devices are placed within a base control logic structure underlying the memory array, then the memory device can be controlled, but performance metrics such as switching speed and power consumption are degraded
Solution Approach 1:
By moving control logic to a vertical stack configuration overlying the memory array, the patent reduces the horizontal separation distance between control logic devices and memory cells. This shortened interconnect path enables faster signal propagation and improves memory cell switching speed while maintaining full control functionality.
3Reliability
If control logic devices are placed within a base control logic structure underlying the memory array, then the memory device can be controlled, but the device complexity and routing requirements increase
Solution Approach 1:
The patent utilizes vertical interconnect structures to route signals between the memory array in the first horizontal plane and the control logic in the second horizontal plane. This vertical routing approach consolidates interconnect paths and reduces the complexity of horizontal routing networks compared to planar integration.
Solution Approach 2:
By segmenting the device into distinct horizontal planes with vertical interconnects, the patent simplifies the routing architecture. Each layer can be independently designed and optimized, reducing the overall routing complexity compared to a monolithic planar structure where all signals must route through the same plane.
Data Source
AI summary
A microelectronic device includes a memory array structure and a control circuitry structure overlying and bonded to the memory array structure. The memory array structure includes memory cells, digit lines, and word lines. The control circuitry structure includes a control circuitry region, digit line contact sections, and word line contact sections. The control circuitry region includes sense amplifier sections including sense amplifiers, and sub-word line driver sections including sub-word line drivers. The digit line contact sections are horizontally adjacent to the sense amplifier sections in a first direction and include contact structures coupled to the sense amplifiers and the digit lines. The word line contact sections are horizontally adjacent to the sub-word line driver sections in a second direction orthogonal to the first direction and include additional contact structures coupled to the sub-word line drivers and the word lines. Additional microelectronic devices, memory devices, and electronic systems are also described.