Bonded Die Interconnect Structure Without Extra Connector Layers
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the physical size of semiconductor devices through stacked and bonded structures, where existing bonding processes are complex and costly, requiring additional connectors and passivation layers that complicate the manufacturing process.
Innovation Solution
A semiconductor structure and manufacturing method involving a first die structure bonded with a second die structure, a conductive via extending through the second die structure, and a conductive member directly coupled with the via, eliminating the need for additional connectors and passivation layers, thereby simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional connectors and passivation layers are used in bonding processes, then electrical connectivity and protection are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the bonding pad structure with the interconnect structure by forming the bonding pad as an integrated part of the interconnect layer during the same fabrication process. This eliminates the need for separate connectors and reduces the number of discrete components, thereby simplifying the manufacturing process while maintaining electrical connectivity.
Solution Approach 2:
The bonding pad structure is designed to serve multiple functions: it provides electrical connectivity for bonding, acts as an interconnect element, and integrates with the passivation structure. This multi-functionality reduces the need for additional dedicated components and simplifies the overall device architecture.
2Reliability
If additional connectors and passivation layers are used in bonding processes, then electrical connectivity and protection are improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple fabrication steps into a single integrated process where the bonding pad, interconnect, and passivation structures are formed simultaneously. This reduces the number of fabrication steps, material deposits, and process variations required, thereby lowering manufacturing cost while ensuring reliable electrical connectivity.
Solution Approach 2:
The bonding pad structure is prepared in advance as part of the interconnect layer during standard CMOS fabrication processes. This preliminary formation eliminates the need for subsequent separate bonding pad creation steps and reduces overall manufacturing complexity and cost.
3Productivity
If minimum feature size is reduced, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes standard CMOS fabrication process parameters and materials that are optimized for existing manufacturing capabilities. By designing the bonding pad structure to work within standard process parameter ranges, the patent achieves high integration density without requiring extreme manufacturing precision beyond current industry standards.
Data Source
AI summary
The semiconductor structure includes a first die structure including a first substrate, a first bonding dielectric disposed over the first substrate, and a first bonding pad surrounded by the first bonding dielectric; a second die structure including a second substrate, an isolation member extending into the second substrate, a second bonding dielectric bonded with the first bonding dielectric, and a second bonding pad surrounded by the second bonding dielectric and bonded with the first bonding pad; a dielectric member disposed over the second die structure; a conductive via extending through the dielectric member, the second substrate and the isolation member; and a conductive member disposed over the dielectric member and at least partially in contact with the conductive via, wherein a first interface between the conductive via and the conductive member is substantially coplanar with a second interface between the conductive member and the dielectric member.