Bonded Memory Cell Stack With Vertical Logic for Dense DRAM Layout
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM, due to processing conditions and the configuration of control logic devices, which limit the reduction of feature dimensions and separation distances, and impede performance enhancements like faster speeds and lower power consumption.
Innovation Solution
The method involves forming a microelectronic device structure with vertically offset control logic devices and memory cells, using a base semiconductor structure with isolation material and contact structures, and attaching a second semiconductor structure to form a connected isolation structure, allowing for reduced horizontal footprint and enhanced areal density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are formed using conventional processing conditions, then the memory array can be fabricated, but the control logic device configurations and performance are limited
Solution Approach 1:
The device is divided into two separate semiconductor structures: a first structure containing the memory array formed under first processing conditions, and a second structure containing the control logic devices formed under second processing conditions. This segmentation allows each portion to be optimized independently, resolving the contradiction between memory array fabrication requirements and control logic device performance needs.
Solution Approach 2:
The control logic devices are positioned in a different spatial dimension (vertical stacking) relative to the memory array, with the second semiconductor structure attached to the first structure. This dimensional separation enables independent optimization of processing conditions for each component while maintaining functional integration.
2Speed
If the quantities, dimensions, and arrangements of control logic devices are increased to improve performance, then memory cell speed and data transfer rates can be enhanced, but the horizontal footprint of the memory device increases
Solution Approach 1:
Control logic devices are moved from the horizontal plane to a vertical stacking arrangement, where the second semiconductor structure containing control logic devices is attached to the first semiconductor structure containing the memory array. This enables multiple control logic devices to be integrated without increasing horizontal footprint, thus improving speed while maintaining compact area.
Solution Approach 2:
The control logic devices are effectively nested within the vertical stack of the memory device structure, with the second semiconductor structure positioned above or adjacent to the first structure. This nesting approach allows dense integration of control logic functionality without expanding the device's horizontal dimensions.
3Area of moving object
If feature dimensions and separation distances are reduced to increase integration density, then device compactness is improved, but processing conditions become more constrained
Solution Approach 1:
The fabrication process is segmented into two independent sequences: forming the memory array under first processing conditions, and forming control logic devices under second processing conditions. This allows feature dimensions to be reduced for high density while each segment maintains its own optimized processing conditions, preserving ease of manufacture.
4Productivity
If conventional base control logic structures are used, then memory array formation is enabled, but areal density and performance are impeded
Solution Approach 1:
The control logic structure transitions from a conventional planar base configuration to a vertical stacked architecture, where the second semiconductor structure is attached to the first structure. This dimensional change enables higher areal density by utilizing the vertical dimension, while the modular nature of the stacked structure keeps the complexity manageable through standardized interfaces.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.