Bonded FinFET Memory Structure for Higher 3D NAND Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D NAND memory chips face challenges with low transistor integration levels, leading to larger chip areas and costly manufacturing processes, as they approach storage density limits.
Innovation Solution
The implementation of a semiconductor device with a first and second semiconductor structure bonded together, featuring a fin field effect transistor in the second well region, which improves transistor performance while reducing chip area by using fin field effect transistors and optimizing gate oxide layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND memory chips are used to increase storage density, then storage capacity is improved, but transistor integration level remains low causing large chip area
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional FinFET structures, utilizing vertical fins extending from the substrate to create additional current flow paths. This dimensional change allows higher transistor integration density within the same chip area, directly addressing the contradiction between storage density and chip area.
Solution Approach 2:
The patent implements multiple well regions (first well region, second well region, third well region) stacked vertically and bonded together, creating a nested multi-layer structure. This nesting approach increases the effective transistor capacity without proportionally increasing the chip footprint, resolving the area-density contradiction.
2Ease of manufacture
If traditional planar processes are used for manufacturing, then manufacturing simplicity is maintained, but storage density approaches upper limit
Solution Approach 1:
The patent divides the semiconductor structure into multiple discrete well regions (first, second, and third well regions) that can be independently formed and then bonded together. This segmentation allows each region to be manufactured using relatively simple planar processes, while the overall stacked structure achieves high storage density.
Solution Approach 2:
The patent forms complete well regions and transistor structures on separate substrates before bonding them together. This preliminary action on individual substrates simplifies the manufacturing process by avoiding complex three-dimensional fabrication, while still achieving high storage density through the final stacked assembly.
3Area of stationary object
If transistor integration level is increased to reduce chip area, then chip area is reduced, but manufacturing process becomes cumbersome and expensive
Solution Approach 1:
The patent segments the high-density transistor structure into multiple identical or similar well regions that can be manufactured using the same process steps. This segmentation into repeatable units reduces manufacturing complexity compared to creating entirely unique three-dimensional structures, while still achieving high integration density.
Solution Approach 2:
The patent creates multiple copies of well regions (first, second, third well regions) with similar structures that are then bonded together. This copying approach simplifies manufacturing by using repeated process steps rather than complex custom fabrication, reducing both process complexity and cost while achieving high transistor integration.
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method thereof, as well as a memory system. The semiconductor device includes a first semiconductor structure comprising a first well region and transistors in the first well region, and a second semiconductor structure bonded with the first semiconductor structure and including a second well region, and fin field effect transistors in the second well region. Each fin field effect transistor includes a fin structure, a gate oxide layer in contact with a top surface and side surfaces of the fin structure, and a gate layer covering the gate oxide layer.