Bonded FPGA-DRAM Structure With 3D Vertical Interconnects
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) face limitations in cost and working frequency due to large chip area consumption and signal transfer delays, such as RC delay from metal routing, which restrict their performance in applications like deep neural networks.
Innovation Solution
A semiconductor device with a programmable logic device core and cache integrated on a bonded chip, featuring a large number of short-distance vertical metal interconnects instead of conventional long-distance metal routing, to achieve higher working frequency, wider data bandwidth, and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional long-distance metal routing is used in FPGAs, then chip area can be reduced, but signal transfer delay increases and working frequency decreases
Solution Approach 1:
The patent transitions from planar (2D) metal routing to three-dimensional (3D) vertical interconnects through wafer bonding. By stacking multiple semiconductor wafers and creating through-wafer vias, the interconnect structure moves into the third dimension, enabling short-distance vertical connections that replace long-distance lateral routing paths.
Solution Approach 2:
The patent divides a single large FPGA chip into multiple smaller semiconductor wafers that are bonded together. Each wafer contains specific logic functions or memory blocks, and the segmentation allows vertical interconnection between these segments, reducing the routing distance within each segment while maintaining overall system functionality.
2Loss of time
If FPGAs use large chip area for routing, then manufacturing cost increases, but signal transfer delay also increases
Solution Approach 1:
The patent employs 3D vertical interconnects through wafer bonding to replace extended 2D metal routing. This dimensional transition creates direct vertical pathways between functional blocks on different wafers, dramatically reducing signal transfer delay without requiring additional lateral routing area that would increase manufacturing cost.
Solution Approach 2:
The patent merges multiple semiconductor wafers into a single bonded chip structure through wafer bonding technology. This combining approach integrates logic functions and memory blocks in close proximity with direct vertical connections, reducing the need for extensive metal routing and associated manufacturing costs while improving signal transfer performance.
3Productivity
If conventional metal routing is used, then device complexity is reduced, but data bandwidth and working frequency are limited
Solution Approach 1:
The patent introduces 3D vertical interconnects that penetrate through multiple wafer layers, creating high-density connection pathways. This dimensional advancement enables parallel data transmission through multiple via layers simultaneously, significantly increasing data bandwidth despite the increased structural complexity of the bonded wafer assembly.
Solution Approach 2:
The patent implements a nested interconnect structure where through-wafer vias are embedded within the bonded wafer stack. Multiple layers of interconnects are nested within each other, with lower-layer vias contained within the overall structure of upper-layer vias, enabling high-density routing with organized complexity that supports increased data bandwidth.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.