Bonded FPGA-DRAM Wafer Stack for Shorter Interconnect Delays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field-programmable gate arrays (FPGAs) are limited by high cost and signal transfer delays due to large chip area consumption and resistive-capacitive (RC) delays from metal routing, which restricts working frequency and efficiency.
Innovation Solution
A semiconductor device with a programmable logic device core and cache integrated with main memory on a bonded chip, utilizing short-distance vertical metal interconnects instead of conventional long-distance metal routing, to achieve higher frequency, wider bandwidth, and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional long-distance metal routing is used in FPGAs, then chip area can be larger, but signal transfer delays increase and working frequency decreases
Solution Approach 1:
The patent transitions from planar (2D) metal routing to three-dimensional (3D) vertical interconnects through wafer bonding. By stacking multiple semiconductor wafers and creating vertical through-silicon vias (TSVs), the interconnect path changes from long horizontal routes to short vertical routes, dramatically reducing routing length and signal delay while enabling higher working frequencies
2Adaptability or versatility
If FPGAs use large chip area, then more logic blocks can be integrated, but manufacturing cost increases
Solution Approach 1:
The patent divides the FPGA into multiple functional modules fabricated on separate semiconductor wafers (logic modules, memory modules, I/O modules). These segmented modules are then bonded together in three-dimensional stacks, allowing independent optimization and manufacturing of each module while reducing overall chip area and manufacturing cost
Solution Approach 2:
The patent implements a hierarchical stacking architecture where multiple functional wafers are nested vertically. Each wafer contains specific functional blocks, and they are stacked like nested dolls to create a compact 3D integrated structure that reduces the footprint area while maintaining high logic block integration
3Manufacturing precision
If conventional bonding methods are used, then manufacturing process is simpler, but manufacturing precision and alignment accuracy decrease
Solution Approach 1:
The patent incorporates alignment marks and positioning structures during the semiconductor device fabrication process, before the bonding step. These pre-formed features enable precise alignment during wafer bonding, ensuring accurate registration of through-silicon vias and interconnects between stacked wafers without requiring complex real-time alignment systems
Data Source
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one first semiconductor structure includes a programmable logic device, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one second semiconductor structure includes an array of DRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one die includes the bonded first and second semiconductor structures.