Bonded Logic-Memory Stack With Vertical Interconnects for Faster Data Transfer
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Solution Overview
Problem
Processors are optimized for sequential processing and lack support for parallelism, limiting their capabilities for high-speed processing, while Field-Programmable Gate Arrays (FPGAs) offer true parallelism but are limited by cost and signal transfer delays.
Innovation Solution
A unified semiconductor device integrating a programmable logic device with heterogeneous memories (DRAM and NAND) on a bonded chip, utilizing short-distance vertical metal interconnects instead of long-distance metal routing, to achieve higher working frequency, wider data bandwidth, and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processors are used for high-speed processing, then sequential processing capability is improved, but parallelism support deteriorates
Solution Approach 1:
The system is divided into multiple processing elements (PEs) that can operate in parallel. Each PE is a self-contained unit capable of independent execution, allowing the system to achieve both high-speed processing and parallelism support by segmenting the processing workload across multiple identical units.
2Adaptability or versatility
If FPGAs are used to achieve true parallelism, then parallelism support is improved, but cost and signal transfer delays worsen
Solution Approach 1:
The invention changes the fundamental parameters of the processing element by using fixed-function PEs with hardwired interconnects instead of programmable logic. This parameter change reduces signal transfer delays and simplifies the device structure while maintaining parallelism capability, thereby reducing cost and complexity compared to FPGAs.
3Length of stationary object
If long-distance metal routing is used in FPGAs, then device coverage is improved, but signal transfer delays worsen
Solution Approach 1:
The invention transitions from two-dimensional planar routing to three-dimensional vertical stacking. By stacking processing elements and interconnect layers vertically, the system achieves long-distance connectivity through the vertical dimension while keeping lateral routing distances short, thereby reducing signal transfer delays.
4Quantity of substance
If heterogeneous memories are integrated on bonded chip, then data bandwidth is improved, but manufacturing complexity worsens
Solution Approach 1:
The memory system is segmented into different types of memory (e.g., SRAM, DRAM, Flash) that are separately optimized and then integrated on the bonded chip. This segmentation allows each memory type to be manufactured using its optimal process while achieving high aggregate bandwidth through their combined operation.
Data Source
Figure 1~2
Figure 3A~3B
Figure 4A~4B
AI summary
A semiconductor device (700) includes a first semiconductor structure (702) including NAND memory cells and a first bonding layer (730) including first bonding contacts (732). The semiconductor device (700) also includes a second semiconductor structure (704) including DRAM cells and a second bonding layer (750) including second bonding contacts (752). The semiconductor device (700) also includes a third semiconductor structure (706) including a programmable logic device (716) and a third bonding layer (726) including third bonding contacts (728). The semiconductor device (700) further includes a first bonding interface (708) between the first and third bonding layers, and a second bonding interface (710) between the second and third bonding layers. The first bonding contacts (732) are in contact with a first set of the third bonding contacts (728) at the first bonding interface (708). The second bonding contacts (752) are in contact with a second set of the third bonding contacts (728) at the second bonding interface (710). The first and second bonding interfaces are in a same plane.