Bonded 3D Memory Array and Circuit Chip for Faster Bit Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional memory devices face challenges with increased bit line capacity and operation speed due to long bit lines, which are exacerbated by the need for deep contacts and additional interconnection layers, leading to potential increases in chip area and operational delays.
Innovation Solution
The semiconductor memory device integrates a circuit chip with a control circuit on a separate substrate, connected to a three-dimensional memory array chip via bonding metals, eliminating the need for deep contacts and reducing interconnection lengths, thereby minimizing chip area and improving operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the control circuit is provided right under the memory array to reduce space factor, then chip area is reduced, but bit lines become substantially long causing increased bit line capacity and decreased operation speed
Solution Approach 1:
The patent divides the memory device into two separate chips: a first chip containing the memory array and a second chip containing the control circuit. This segmentation allows each chip to be optimized independently, preventing the control circuit from being positioned directly under the array which would create long bit lines. The separation maintains short interconnection paths while reducing overall chip area through vertical stacking.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked configuration. By placing the control circuit on a separate chip and bonding it to the memory array chip, the design moves the control circuit from the two-dimensional plane under the array to a separate vertical layer, eliminating long bit lines while maintaining compact form factor.
2Reliability
If deep contacts and additional interconnection layers are added to connect bit lines to transistors under the array, then connectivity is achieved, but manufacturing complexity and chip area increase
Solution Approach 1:
The patent segments the interconnection structure by placing different components on separate chips. The memory array chip contains bit lines and memory cells, while the control circuit chip contains transistors. This eliminates the need for deep contacts and complex interconnection layers that would be required to connect elements within a single monolithic chip, significantly reducing manufacturing complexity.
Solution Approach 2:
The patent extracts the control circuit from the memory array chip and places it on a separate chip. This extraction eliminates the need for complex deep contact structures and additional interconnection layers that would be necessary to connect bit lines to transistors located under the array in a monolithic structure.
3Reliability
If bit lines are made substantially long to reach transistors under the array, then connectivity is achieved, but bit line capacity increases and operation speed decreases
Solution Approach 1:
By segmenting the device into separate chips, the patent eliminates the need for long bit lines that would extend from the memory array to transistors located under the array. The bit lines remain localized on the memory array chip, maintaining low capacitance while achieving connectivity through direct bonding interfaces between chips.
Data Source
AI summary
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.