Bonded Memory Chip Insulation Layout for Faster I/O Signals
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Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high-speed operations due to parasitic capacitance between bonding electrodes, which can lower operation speed and mechanical strength, and existing solutions with low dielectric constant insulating layers may compromise mechanical integrity.
Innovation Solution
The semiconductor storage device incorporates a dual insulating layer configuration, where a low dielectric constant insulating layer 107 is placed near bonding electrodes on the chip's surface and a higher dielectric constant insulating layer 108 is positioned farther away, reducing parasitic capacitance while enhancing mechanical strength, and ensures equal wiring lengths for high-speed signal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low dielectric constant insulating layer is used near bonding electrodes to reduce parasitic capacitance, then operation speed is improved, but mechanical strength is compromised
Solution Approach 1:
The insulating layer is divided into multiple segments with different dielectric constants positioned at different distances from the bonding electrodes. The first insulating layer with lower dielectric constant is positioned closer to the bonding electrodes to reduce parasitic capacitance, while the second insulating layer with higher dielectric constant is positioned farther away to provide mechanical strength support.
Solution Approach 2:
Different regions of the insulating structure are assigned different dielectric constants based on their functional requirements. The region closer to the bonding electrodes uses material with lower dielectric constant for electrical performance, while the region farther away uses material with higher dielectric constant for mechanical support.
2Quantity of substance
If bonding electrodes are placed closer together to increase density, then device integration is improved, but parasitic capacitance increases lowering operation speed
Solution Approach 1:
The insulating layers are strategically positioned to provide different dielectric constant characteristics in different spatial locations. The first insulating layer with lower dielectric constant is placed in the critical region near the bonding electrodes to minimize parasitic capacitance, enabling closer electrode spacing without sacrificing speed.
3Speed
If wiring lengths are made equal to ensure consistent signal delays, then high-speed operation is achieved, but wiring layer design freedom is reduced
Solution Approach 1:
The dielectric constant parameter of the insulating layers is changed as a function of distance from the bonding electrodes. This parameter variation compensates for differences in wiring path lengths, allowing flexible wiring layer design while maintaining consistent signal delays through the combined effect of different dielectric constants and path lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, maintains mechanical strength, and ensures consistent high-speed signal operations by aligning signal delays within a predetermined range, enhancing the design freedom in wiring layers.
Implementation Method 1
a first insulating layer 107 with a lower dielectric constant than a second insulating layer 108 and positioned closer to the plurality of bonding electrodes PI1 than the second insulating layer 108
Data Source
AI summary
A semiconductor storage device includes first and second chips. The first chip has first bonding electrodes on a first surface. The second chip has second bonding electrodes on a second surface. The first surface is bonded to the second surface and the first bonding electrodes are electrically connected to the second bonding electrodes. One of the first and second chips has a first bonding pad electrode connectable to a bonding wire for data input/output. A first one of the first bonding electrodes is electrically connected to the first bonding pad electrode. The first chip has, on the first surface, a first insulating layer surrounding the first one of the first bonding electrodes and a second insulating layer that is farther from the first one of the first bonding electrodes than the first insulating layer and formed of a material different from that of the first insulating layer.