Bonded Multi-Die Memory Circuit for High Density and Low Latency
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Solution Overview
Problem
The manufacturing of 3-dimensional thin-film memory arrays poses challenges due to thermal cycles that degrade low-voltage logic circuits, affecting yield and performance, and existing hybrid bonding methods compromise the scalability and performance of low-voltage transistors.
Innovation Solution
The integration of quasi-volatile or non-volatile memory circuits on a first semiconductor die and faster memory circuits on a second die, using advanced manufacturing nodes for low-voltage transistors on the companion chip, while decoupling them from high-voltage and medium-voltage transistors, allows for high-density, low-latency memory circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3-dimensional thin-film memory arrays are manufactured using thermal cycles, then high-density memory storage is achieved, but low-voltage logic circuits are degraded
Solution Approach 1:
The patent divides the memory circuit into separate high-voltage memory arrays and low-voltage logic circuits, allowing them to be manufactured independently with appropriate process conditions. The high-voltage memory can withstand thermal cycles while the low-voltage logic circuits are protected from degradation by being fabricated separately at advanced nodes.
Solution Approach 2:
The low-voltage logic circuits are extracted from the high-voltage memory manufacturing process. By separating the fabrication processes, the low-voltage circuits are removed from the thermal cycle environment that degrades their performance, while the high-voltage memory arrays can still be manufactured with high density using thermal cycles.
2Device complexity
If hybrid bonding methods are used to integrate memory circuits, then circuit integration is achieved, but scalability and performance of low-voltage transistors are compromised
Solution Approach 1:
The patent segments the integrated circuit into separate high-voltage and low-voltage die or circuit regions that are bonded together. This segmentation allows the low-voltage transistors to be manufactured at advanced nodes with optimized processes, while still achieving full circuit integration through hybrid bonding of the separate regions.
Solution Approach 2:
Different regions of the integrated circuit are given different manufacturing qualities - high-voltage regions use robust processes suitable for high-voltage transistors, while low-voltage regions use advanced manufacturing nodes optimized for high-performance low-voltage transistors. The hybrid bonding connects these regions with appropriate local interconnect structures.
Data Source
AI summary
An integrated circuit includes a first semiconductor die having first memory circuits and a second semiconductor die having second memory circuits, the second memory circuits having a write latency shorter than that of the first memory circuits. The first semiconductor die and the second semiconductor die are interconnected by interconnections formed by wafer-level or chip-level bonding between the first and second semiconductor dies. The second semiconductor die includes an on-chip control circuit that controls operations of the first memory circuits and the second memory circuits to transfer data between the first memory circuits and the second memory circuits.