Bonded Memory Chip Layout With Pre-Bond Die Sorting

Solution Overview

Problem

The challenge of integrating high-capacity and high-integration memory devices with 3D memory cell arrays and peripheral circuits in a vertical configuration, while ensuring effective electrical operation and data integrity.

Innovation Solution

A memory device comprising a memory chip with a 3D memory cell array and a peripheral circuit chip with a 2D test cell array, connected via bonding pads, where the peripheral circuit chip undergoes electrical die sorting and information data reading before bonding to ensure functional integrity, followed by fabrication into a complete memory device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a 3D memory cell array is integrated with peripheral circuits in a vertical configuration to increase capacity and integration, then memory device capacity and integration are improved, but ensuring effective electrical operation and data integrity becomes more difficult

Engineering Contradiction:

Improvememory device capacityVSAvoidelectrical operation and data integrity

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The memory device is divided into separate memory chip and peripheral circuit chip components, each fabricated and tested independently before being bonded together. This segmentation allows for specialized optimization of each component while maintaining overall system reliability through modular architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Electrical die sorting and information data reading operations are performed on the peripheral circuit chip before bonding to the memory chip. This preliminary testing ensures that only functional components are integrated, preventing propagation of defects and ensuring data integrity in the final assembled device.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If electrical die sorting and information data reading are performed on the peripheral circuit chip before bonding, then reliability of the memory device is improved, but manufacturing time and process complexity increase

Engineering Contradiction:

Improvefunctional integrityVSAvoidmanufacturing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The electrical die sorting and information data reading operations are performed on the peripheral circuit chip during the manufacturing process before bonding to the memory chip. This preliminary action ensures that only functional components are integrated, preventing propagation of defects and ensuring data integrity in the final assembled device.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The electrical die sorting and information data reading operations are integrated into the manufacturing flow as combined process steps performed on the peripheral circuit chip before bonding. This merging of testing operations into the manufacturing sequence ensures reliability without requiring separate post-assembly testing phases.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If separate memory chip and peripheral circuit chip are bonded together to form complete memory device, then integration density is improved, but manufacturing process complexity increases

Engineering Contradiction:

Improveintegration densityVSAvoidmanufacturing process

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The memory device is divided into separate memory chip and peripheral circuit chip components, each fabricated and tested independently before being bonded together. This segmentation allows for specialized optimization of each component while maintaining overall system reliability through modular architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Electrical die sorting and information data reading operations are performed on the peripheral circuit chip before bonding to the memory chip. This preliminary testing ensures that only functional components are integrated, preventing propagation of defects and ensuring data integrity in the final assembled device.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250309166A1Memory device including memory chip and peripheral memory chip and method of manufacturing the memory device

Publication Date: 2025.10.02 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.