Bonded 3D Memory Stack with Separation Structure for Reliable Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity while maintaining reliability and integration, particularly in electronic systems that require large data storage.
Innovation Solution
A semiconductor device is designed with a semiconductor substrate, a peripheral circuit structure, and a cell array structure. The cell array structure includes a stack structure, separation structures penetrating the stack, vertical channel patterns, a source conductive pattern, an upper dielectric layer, and an upper via. This configuration allows for increased data storage capacity and improved reliability by separating the peripheral circuits from the cell array structure during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If peripheral circuits and cell array structure are integrated on the same substrate, then device complexity is reduced, but manufacturing precision and reliability deteriorate due to simultaneous processing constraints
Solution Approach 1:
The semiconductor device is divided into two separate structures: a peripheral circuit structure and a cell array structure. These structures are manufactured independently on separate substrates and then bonded together through bonding pads, allowing each to be optimized and processed separately while maintaining overall integration.
2Productivity
If data storage capacity is increased by adding more memory cells, then productivity improves, but reliability deteriorates due to increased defect probability
Solution Approach 1:
The memory device is segmented into peripheral circuit region and cell array region, with the cell array further divided into multiple blocks. This segmentation allows independent optimization of each region and enables replacement or repair of defective blocks without affecting the entire device.
Solution Approach 2:
The invention changes the architectural parameter from traditional planar layout to a three-dimensional stacked architecture with vertical channels penetrating through multiple dielectric layers, increasing storage capacity per unit area while maintaining manufacturing control.
3Productivity
If three-dimensional stacked architecture is used to increase storage capacity, then productivity improves, but device complexity increases
Solution Approach 1:
The invention transitions from two-dimensional planar memory architecture to three-dimensional stacked architecture by introducing vertical channels that penetrate through multiple horizontally stacked dielectric layers, effectively utilizing the third dimension to increase storage capacity.
Solution Approach 2:
The structure employs nested arrangements where vertical channels are embedded within stacked dielectric layers, and bonding pads are integrated within the stacked architecture, allowing multiple functional elements to occupy overlapping spatial regions.
Data Source
AI summary
A semiconductor device may include a peripheral circuit structure first bonding pads connected to peripheral circuits on a semiconductor substrate; and a cell array structure including second bonding pads bonded to the first bonding pads. The cell array structure may include a separation structure penetrating a stack structure, vertical channel patterns penetrating the stack structure, a source conductive pattern connected to the vertical channel patterns on the stack structure, an upper dielectric layer covering the source conductive pattern, and an upper via that penetrates the upper dielectric layer. The stack structure may include interlayer dielectric layers and conductive patterns that are vertically alternately stacked. The separation structure may include a stop pattern on a dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. The upper via may connect to the source conductive pattern on the stop pattern.