Bonded Memory Chip Layout for Split High- and Low-Voltage Transistors
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Solution Overview
Problem
The integration of high-speed semiconductor storage devices requires separate formation of high voltage and low voltage transistors on different wafers to prevent short-channel effects and manage thermal processes, while also reducing dead space and improving alignment accuracy during bonding, which is challenging due to the complexity of layouts and varying transistor requirements.
Innovation Solution
The configuration involves forming the memory cell array and high voltage transistors on one chip (CM) and low voltage transistors on another chip (CP), with optimized bonding electrode placement and reduced alignment requirements, allowing for more accurate bonding and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If high voltage transistors and low voltage transistors are formed on the same wafer, then device integration is simplified, but short-channel effects increase and thermal process management becomes difficult
Solution Approach 1:
The patent divides the transistor formation process into two separate wafers: one for high voltage transistors and another for low voltage transistors. This segmentation allows independent optimization of each transistor type, preventing short-channel effects in low voltage transistors while enabling proper thermal process management for high voltage transistors, thus resolving the contradiction between process simplification and reliability.
2Reliability
If high voltage transistors and low voltage transistors are formed on separate wafers, then short-channel effects are reduced, but alignment accuracy during bonding becomes more critical
Solution Approach 1:
The patent introduces alignment marks as intermediary features on both wafers that facilitate precise alignment during the bonding process. These marks serve as reference points that guide the bonding process, reducing the criticality of alignment accuracy while maintaining the benefits of separate wafer formation for short-channel effect control.
3Temperature
If separate wafers are used for high voltage and low voltage transistors, then thermal process management improves, but dead space increases due to layout complexity
Solution Approach 1:
The patent merges the high voltage transistor wafer and low voltage transistor wafer through a bonding process that integrates them into a unified device structure. This merging approach allows independent thermal process optimization for each wafer type while reducing dead space by eliminating the need for separate packaging and interconnections that would otherwise be required for completely discrete components.
Data Source
AI summary
A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction.