3D Integrated Circuit Structure Using Bonded Metal Planes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional integrated circuits face physical limits in integration density and increased interconnections lead to higher circuit resistance-capacitance delay and power consumption, necessitating the development of three-dimensional integrated circuits with through silicon vias for improved device density and reduced wire length.
Innovation Solution
The method involves aligning and bonding metallic layers on two semiconductor structures with an insulator layer, forming an electrically isolated metallic layer, and creating a through silicon via in one structure to connect with the other, using conductive materials while maintaining electrical isolation from the bonded layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more devices are integrated into one chip to improve device density, then integration density increases, but the number and length of interconnections increase leading to higher RC delay and power consumption
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple semiconductor wafers. This dimensional change allows devices to be arranged in multiple layers, significantly increasing device density while reducing the lateral distance signals must travel, thereby decreasing RC delay and power consumption associated with long interconnections.
Solution Approach 2:
The patent divides a single large chip into multiple smaller semiconductor wafers that are stacked vertically. Each wafer contains a subset of devices and interconnections. This segmentation reduces the interconnection length within each layer while the vertical stacking provides additional routing paths, overall reducing the total RC delay and power consumption compared to a single monolithic chip.
2Quantity of substance
If more devices are integrated into one chip to improve device density, then integration density increases, but circuit resistance-capacitance delay increases
Solution Approach 1:
By stacking wafers vertically, the patent creates three-dimensional routing paths that shorten the lateral distance signals must travel. This reduces the resistance and capacitance of interconnections, thereby decreasing RC delay while achieving high device density through vertical stacking rather than lateral expansion.
Solution Approach 2:
Dividing the circuit into multiple stacked wafers segments the interconnection network. Signals only need to travel across smaller distances within each wafer layer, and vertical vias provide direct routing between layers. This segmentation reduces overall interconnection length and RC delay compared to long lateral routes in a single large chip.
3Reliability
If metallic layers are bonded directly to form electrical connections, then electrical connectivity is achieved, but electrical isolation between bonded structures is lost
Solution Approach 1:
The patent applies different functional properties to different regions of the metallic layers. In some regions, metallic layers are bonded to form electrical connections between wafers. In other regions, metallic layers are left unbonded or interrupted to maintain electrical isolation. This local differentiation of bonding properties allows simultaneous achievement of electrical connectivity where needed and electrical isolation where required.
Solution Approach 2:
The patent extracts or removes portions of the metallic layers at specific locations to create gaps or interruptions. These removed sections prevent unwanted electrical connections between bonded wafers, maintaining electrical isolation in regions where it is required while preserving connectivity in regions where metallic layers remain intact and bonded.
4Quantity of substance
If through silicon vias are formed to interconnect devices on first and second wafers, then 3D integration is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming through-silicon vias and preparing metallic bonding layers on each wafer before the actual bonding process. This pre-processing allows for precise alignment and reduces the complexity of the bonding step itself, as the interconnection structures are already in place and ready for connection when wafers are stacked and bonded together.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density, reduces wire length, and decreases the number of vias, potentially making 3D integrated circuit technology the next generation standard by addressing the limitations of 2D circuits.
Implementation Method 1
contacting and bonding the metallic layers of the first and second semiconductor structures to each other
Data Source
AI summary
A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.