Bonded NAND Memory Layout for Higher Bandwidth and Lower Parasitics
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Solution Overview
Problem
Current NAND-type flash memory systems face challenges in increasing communication bandwidth and storage capacity while minimizing parasitic components and costs, particularly due to the separation of memory controllers and semiconductor memory devices, which leads to inefficiencies in data transfer and chip design.
Innovation Solution
The proposed memory system integrates the memory controller and input/output module within the CMOS chip, reducing the distance between components and parasitic components, and uses a bonded structure to increase the area occupied by the memory cell array, allowing for higher bus widths without increasing chip pins or wires, thus enhancing communication speed and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the memory controller and semiconductor memory device are separated into different chips, then the chip design and manufacturing become simpler, but the communication bandwidth is limited and parasitic components increase
Solution Approach 1:
The patent merges the memory controller and input/output module onto the same CMOS chip as the memory cell array. This integration eliminates the need for separate chips and inter-chip connections, thereby increasing communication bandwidth and reducing parasitic components while maintaining manufacturing feasibility through advanced CMOS processes.
Solution Approach 2:
The patent transitions from a two-chip architecture to a three-dimensional stacked architecture where the memory cell array and controller are vertically integrated. This dimensional change allows for higher communication bandwidth without increasing the lateral footprint, effectively resolving the bandwidth limitation while keeping the chip design manageable.
2Productivity
If the memory controller is integrated with the memory cell array on the same chip, then communication bandwidth increases and parasitic components are reduced, but the chip design becomes more complex
Solution Approach 1:
The patent segments the integrated chip into distinct functional regions: a memory cell array region and a controller region. This segmentation allows for independent optimization of each region's design and manufacturing processes, reducing overall chip design complexity while maintaining the benefits of integration for communication bandwidth and parasitic reduction.
3Speed
If the bus width is increased to enhance communication speed, then more pins or wires are required, but the chip pins and wire count are limited
Solution Approach 1:
The patent utilizes vertical stacking to increase the effective bus width without proportionally increasing the number of external pins. By stacking memory cells and control circuits in three dimensions, the system achieves higher communication speed while keeping the lateral pin count manageable, effectively resolving the contradiction between speed and pin complexity.
Data Source
AI summary
According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.