Semiconductor Package Bonded Pad Structure for Stacked Chip Reliability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high integration and high-speed performance while maintaining reliable operation, particularly in stacked semiconductor chip configurations.
Innovation Solution
The semiconductor package design includes a first semiconductor chip and multiple stacked second semiconductor chips, connected by bonded pads that penetrate through various layers, with specific alignment patterns and cover layers to ensure reliable electrical connections and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked to achieve high integration, then the integration density increases, but the reliability of electrical connections between stacked chips deteriorates
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked configuration, enabling high integration density while maintaining connection reliability through vertical bonding interfaces. Multiple chips are stacked in the vertical dimension with bonded pads connecting corresponding pads across chip interfaces.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically, with each chip containing semiconductor elements and bonded pads. The bonded pads of upper chips nest with the corresponding pads of lower chips, creating a hierarchical nested arrangement that achieves high integration while maintaining reliable electrical connections.
2Reliability
If bonded pads are made longer to penetrate through cover layers, then electrical connection is improved, but the risk of damage to cover layers increases
Solution Approach 1:
The patent performs preliminary actions by forming reinforcement structures within the cover layers before creating the bonded pad holes. These reinforcement structures are pre-positioned to provide support during the hole formation process and subsequent bonding operations, preventing cover layer damage while enabling reliable electrical connections.
Solution Approach 2:
The patent implements cushioning measures by incorporating reinforcement structures that absorb and distribute mechanical stresses during the bonding process. These structures are placed beforehand in strategic positions to cushion the cover layers against damage from the penetrating bonded pads, ensuring both connection reliability and cover layer integrity.
Data Source
AI summary
A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.