Bonded Semiconductor Pad Density Layout for Void-Free Hybrid Bonding
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Solution Overview
Problem
Hybrid bonding of semiconductor layers is prone to connection failures due to the formation of voids caused by insufficient precision, leading to unreliable bonding.
Innovation Solution
The use of a semiconductor device design with varying metal pad sizes and densities on the bonding surface, where smaller metal pads are placed between regions of higher and zero metal density, helps prevent voids by smoothing the topology of the bonded surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hybrid bonding is performed with standard metal pad configurations, then bonding process can be completed, but voids form between semiconductor layers due to insufficient precision
Solution Approach 1:
The patent applies local quality by varying the size of metal pads at different locations on the bonding surface. Specifically, a first metal pad with a first size is provided at a first location, while a second metal pad with a second size (smaller than the first size) is provided at a second location. This local variation in metal pad dimensions allows for differential compensation of topology changes across the bonding interface, addressing the precision issue locally rather than requiring uniform high precision across the entire bonding surface.
2Ease of manufacture
If metal pads are uniformly sized and distributed, then manufacturing is simplified, but voids occur due to abrupt topology changes at bonding interface
Solution Approach 1:
The patent implements parameter changes by modifying the size parameter of metal pads based on their location. The first metal pad has a first size and the second metal pad has a second size that is smaller than the first size. This gradual parameter change creates a more progressive topology transition at the bonding interface, reducing abrupt changes that lead to void formation, while still maintaining a relatively simple fabrication process.
3Manufacturing precision
If bonding precision is increased to prevent voids, then void formation is reduced, but the complexity of the bonding process increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring metal pads of different sizes at different locations on the bonding surface before the bonding process occurs. The first metal pad with first size and second metal pad with second size are arranged in advance to compensate for expected topology changes during bonding. This preliminary structural design reduces the need for extremely high bonding precision and complex process control during the actual bonding operation.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer including a wire and an electrical element; and a plurality of metal pads on a surface of the semiconductor layer, wherein the plurality of metal pads includes a first metal pad and a second metal pad, wherein the second metal pad is smaller in surface area or diameter on the surface of the semiconductor layer than the first metal pad, and wherein the second metal pad is between a first region of the surface of the semiconductor layer where the first metal pad is and a second region of the surface of the semiconductor layer where a surface metal density is zero (0).